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[Qemu-devel] [PATCH 01/13] target-mips: fix {D, W}RGPR in microMIPS
From: |
Yongbok Kim |
Subject: |
[Qemu-devel] [PATCH 01/13] target-mips: fix {D, W}RGPR in microMIPS |
Date: |
Fri, 12 Jun 2015 15:02:11 +0100 |
rt, rs were swapped
Signed-off-by: Yongbok Kim <address@hidden>
---
target-mips/translate.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index f6ae0d3..d4a530d 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -12749,12 +12749,12 @@ static void gen_pool32axf (CPUMIPSState *env,
DisasContext *ctx, int rt, int rs)
case RDPGPR:
check_cp0_enabled(ctx);
check_insn(ctx, ISA_MIPS32R2);
- gen_load_srsgpr(rt, rs);
+ gen_load_srsgpr(rs, rt);
break;
case WRPGPR:
check_cp0_enabled(ctx);
check_insn(ctx, ISA_MIPS32R2);
- gen_store_srsgpr(rt, rs);
+ gen_store_srsgpr(rs, rt);
break;
default:
goto pool32axf_invalid;
--
1.7.5.4
- Re: [Qemu-devel] [PATCH 09/13] target-mips: microMIPS32 R6 POOL32F instructions, (continued)
- [Qemu-devel] [PATCH 11/13] target-mips: microMIPS32 R6 Major instructions, Yongbok Kim, 2015/06/12
- [Qemu-devel] [PATCH 10/13] target-mips: microMIPS32 R6 POOL32{I, C} instructions, Yongbok Kim, 2015/06/12
- [Qemu-devel] [PATCH 13/13] target-mips: add mips32r6-generic CPU definition, Yongbok Kim, 2015/06/12
- [Qemu-devel] [PATCH 02/13] target-mips: add microMIPS TLBINV, TLBINVF, Yongbok Kim, 2015/06/12
- [Qemu-devel] [PATCH 12/13] target-mips: microMIPS32 R6 POOL16{A, C} instructions, Yongbok Kim, 2015/06/12
- [Qemu-devel] [PATCH 01/13] target-mips: fix {D, W}RGPR in microMIPS,
Yongbok Kim <=
- [Qemu-devel] [PATCH 06/13] target-mips: add microMIPS32 R6 opcode enum, Yongbok Kim, 2015/06/12
- [Qemu-devel] [PATCH 07/13] target-mips: microMIPS32 R6 branches and jumps, Yongbok Kim, 2015/06/12
- [Qemu-devel] [PATCH 05/13] target-mips: signal RI for removed instructions in microMIPS R6, Yongbok Kim, 2015/06/12