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[Qemu-devel] [PATCH target-arm v2 11/13] target-arm: Add support for Cor
From: |
Peter Crosthwaite |
Subject: |
[Qemu-devel] [PATCH target-arm v2 11/13] target-arm: Add support for Cortex-R5 |
Date: |
Fri, 12 Jun 2015 12:10:52 -0700 |
Introduce a CPU model for the Cortex R5 processor. ARMv7 with MPU,
and both thumb and ARM div instructions.
Also implement dummy ATCM and BTCM. These CPs are defined for R5 but
don't have a lot of meaning in QEMU yet. Raz them so the guest can
proceed if they are read. The TCM registers will return a size of 0,
indicating no TCM.
Signed-off-by: Peter Crosthwaite <address@hidden>
---
Based loosely on an old patch of Andreas' for the cortex-r4.
changed since v1:
Squashed in R5 specific CP regs patch
Reordered to be after supporting patches
set mp_is_up
target-arm/cpu.c | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 1ef2f03..b1c20c2 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -825,6 +825,43 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
}
+static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
+ /* Dummy the TCM region regs for the moment */
+ { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_CONST },
+ { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
+ .access = PL1_RW, .type = ARM_CP_CONST },
+ REGINFO_SENTINEL
+};
+
+static void cortex_r5_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
+ set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
+ set_feature(&cpu->env, ARM_FEATURE_V7MP);
+ set_feature(&cpu->env, ARM_FEATURE_MPU);
+ cpu->midr = 0x411fc153; /* r1p3 */
+ cpu->id_pfr0 = 0x0131;
+ cpu->id_pfr1 = 0x001;
+ cpu->id_dfr0 = 0x010400;
+ cpu->id_afr0 = 0x0;
+ cpu->id_mmfr0 = 0x0210030;
+ cpu->id_mmfr1 = 0x00000000;
+ cpu->id_mmfr2 = 0x01200000;
+ cpu->id_mmfr3 = 0x0211;
+ cpu->id_isar0 = 0x2101111;
+ cpu->id_isar1 = 0x13112111;
+ cpu->id_isar2 = 0x21232141;
+ cpu->id_isar3 = 0x01112131;
+ cpu->id_isar4 = 0x0010142;
+ cpu->id_isar5 = 0x0;
+ cpu->mp_is_up = true;
+ define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
+}
+
static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
{ .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -1216,6 +1253,7 @@ static const ARMCPUInfo arm_cpus[] = {
{ .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
{ .name = "cortex-m3", .initfn = cortex_m3_initfn,
.class_init = arm_v7m_class_init },
+ { .name = "cortex-r5", .initfn = cortex_r5_initfn },
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
--
2.4.3.3.g905f831
- [Qemu-devel] [PATCH target-arm v2 04/13] arm: Refactor get_phys_addr FSR return mechanism, (continued)
- [Qemu-devel] [PATCH target-arm v2 04/13] arm: Refactor get_phys_addr FSR return mechanism, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 05/13] arm: Implement uniprocessor with MP config, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 06/13] arm: Add has-mpu property, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 07/13] target-arm/helper.c: define MPUIR register, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 08/13] arm: helper: rename get_phys_addr_mpu, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 09/13] target-arm: Add registers for PMSAv7, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 11/13] target-arm: Add support for Cortex-R5,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH target-arm v2 10/13] target-arm: Implement PMSAv7 MPU, Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 12/13] arm: xlnx-zynqmp: Preface CPU variables with "apu", Peter Crosthwaite, 2015/06/12
- [Qemu-devel] [PATCH target-arm v2 13/13] arm: xlnx-zynqmp: Add 2xCortexR5 CPUs, Peter Crosthwaite, 2015/06/12
- Re: [Qemu-devel] [PATCH target-arm v2 00/13] ARM Cortex R5 Support, Peter Maydell, 2015/06/15