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[Qemu-devel] [PATCH v2] target-i386: emulate CPUID level of real hardwar
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From: |
Radim Krčmář |
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Subject: |
[Qemu-devel] [PATCH v2] target-i386: emulate CPUID level of real hardware |
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Date: |
Fri, 19 Jun 2015 13:20:40 +0200 |
W10 insider has a bug where it ignores CPUID level and interprets
CPUID.(EAX=07H, ECX=0H) incorrectly, because CPUID in fact returned
CPUID.(EAX=04H, ECX=0H); this resulted in execution of unsupported
instructions.
While it's a Windows bug, there is no reason to emulate incorrect level.
I have used http://instlatx64.atw.hu/ as a source of CPUID and checked
that it matches Penryn Xeon X5472, Westmere Xeon W3520, SandyBridge
i5-2540M, and Haswell i5-4670T.
kvm64 and qemu64 were bumped to 0xD to allow all available features for
them (and to avoid the same Windows bug).
Signed-off-by: Radim Krčmář <address@hidden>
---
v2:
* maintained compatibility for old (< 2.4) machine types [Paolo]
* dropped automatic increase to 0xd, for compatibility [Eduardo]
I devote this code to copy&paste.
hw/i386/pc_piix.c | 18 ++++++++++++++++
hw/i386/pc_q35.c | 18 ++++++++++++++++
target-i386/cpu.c | 63 ++++++++++++++++++++++++++++++++++++++-----------------
target-i386/cpu.h | 3 +++
4 files changed, 83 insertions(+), 19 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index e142f75649d8..c335e230277b 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -307,6 +307,24 @@ static void pc_init1(MachineState *machine)
static void pc_compat_2_3(MachineState *machine)
{
savevm_skip_section_footers();
+
+ x86_cpu_compat_set_level("qemu64", 4);
+ x86_cpu_compat_set_level("kvm64", 5);
+ x86_cpu_compat_set_level("pentium3", 2);
+ x86_cpu_compat_set_level("n270", 5);
+ x86_cpu_compat_set_level("Conroe", 4);
+ x86_cpu_compat_set_level("Penryn", 4);
+ x86_cpu_compat_set_level("Nehalem", 4);
+
+ x86_cpu_compat_set_xlevel("n270", 0x8000000a);
+ x86_cpu_compat_set_xlevel("Penryn", 0x8000000a);
+ x86_cpu_compat_set_xlevel("Nehalem", 0x8000000a);
+ x86_cpu_compat_set_xlevel("Westmere", 0x8000000a);
+ x86_cpu_compat_set_xlevel("SandyBridge", 0x8000000a);
+ x86_cpu_compat_set_xlevel("Haswell", 0x8000000a);
+ x86_cpu_compat_set_xlevel("Haswell-noTSX", 0x8000000a);
+ x86_cpu_compat_set_xlevel("Broadwell", 0x8000000a);
+ x86_cpu_compat_set_xlevel("Broadwell-noTSX", 0x8000000a);
}
static void pc_compat_2_2(MachineState *machine)
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 082cd93bb2d7..99bfd6d6f288 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -291,6 +291,24 @@ static void pc_q35_init(MachineState *machine)
static void pc_compat_2_3(MachineState *machine)
{
savevm_skip_section_footers();
+
+ x86_cpu_compat_set_level("qemu64", 4);
+ x86_cpu_compat_set_level("kvm64", 5);
+ x86_cpu_compat_set_level("pentium3", 2);
+ x86_cpu_compat_set_level("n270", 5);
+ x86_cpu_compat_set_level("Conroe", 4);
+ x86_cpu_compat_set_level("Penryn", 4);
+ x86_cpu_compat_set_level("Nehalem", 4);
+
+ x86_cpu_compat_set_xlevel("n270", 0x8000000a);
+ x86_cpu_compat_set_xlevel("Penryn", 0x8000000a);
+ x86_cpu_compat_set_xlevel("Nehalem", 0x8000000a);
+ x86_cpu_compat_set_xlevel("Westmere", 0x8000000a);
+ x86_cpu_compat_set_xlevel("SandyBridge", 0x8000000a);
+ x86_cpu_compat_set_xlevel("Haswell", 0x8000000a);
+ x86_cpu_compat_set_xlevel("Haswell-noTSX", 0x8000000a);
+ x86_cpu_compat_set_xlevel("Broadwell", 0x8000000a);
+ x86_cpu_compat_set_xlevel("Broadwell-noTSX", 0x8000000a);
}
static void pc_compat_2_2(MachineState *machine)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 4e7cdaaaa57e..7dabf7de25ea 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -677,7 +677,7 @@ struct X86CPUDefinition {
static X86CPUDefinition builtin_x86_defs[] = {
{
.name = "qemu64",
- .level = 4,
+ .level = 0xd,
.vendor = CPUID_VENDOR_AMD,
.family = 6,
.model = 6,
@@ -753,7 +753,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
},
{
.name = "kvm64",
- .level = 5,
+ .level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 15,
.model = 6,
@@ -864,7 +864,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
},
{
.name = "pentium3",
- .level = 2,
+ .level = 3,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 7,
@@ -889,8 +889,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
},
{
.name = "n270",
- /* original is on level 10 */
- .level = 5,
+ .level = 10,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 28,
@@ -910,12 +909,12 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT2_NX,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_LAHF_LM,
- .xlevel = 0x8000000A,
+ .xlevel = 0x80000008,
.model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
},
{
.name = "Conroe",
- .level = 4,
+ .level = 10,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 15,
@@ -932,12 +931,12 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_LAHF_LM,
- .xlevel = 0x8000000A,
+ .xlevel = 0x80000008,
.model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
},
{
.name = "Penryn",
- .level = 4,
+ .level = 10,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 23,
@@ -955,12 +954,12 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_LAHF_LM,
- .xlevel = 0x8000000A,
+ .xlevel = 0x80000008,
.model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
},
{
.name = "Nehalem",
- .level = 4,
+ .level = 11,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 26,
@@ -978,7 +977,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_LAHF_LM,
- .xlevel = 0x8000000A,
+ .xlevel = 0x80000008,
.model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
},
{
@@ -1002,7 +1001,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
.features[FEAT_8000_0001_ECX] =
CPUID_EXT3_LAHF_LM,
- .xlevel = 0x8000000A,
+ .xlevel = 0x80000008,
.model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
},
{
@@ -1031,7 +1030,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT3_LAHF_LM,
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT,
- .xlevel = 0x8000000A,
+ .xlevel = 0x80000008,
.model_id = "Intel Xeon E312xx (Sandy Bridge)",
},
{
@@ -1063,7 +1062,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT3_LAHF_LM,
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT,
- .xlevel = 0x8000000A,
+ .xlevel = 0x80000008,
.model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
},
{
@@ -1097,7 +1096,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT,
- .xlevel = 0x8000000A,
+ .xlevel = 0x80000008,
.model_id = "Intel Core Processor (Haswell, no TSX)",
}, {
.name = "Haswell",
@@ -1131,7 +1130,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_7_0_EBX_RTM,
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT,
- .xlevel = 0x8000000A,
+ .xlevel = 0x80000008,
.model_id = "Intel Core Processor (Haswell)",
},
{
@@ -1167,7 +1166,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_7_0_EBX_SMAP,
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT,
- .xlevel = 0x8000000A,
+ .xlevel = 0x80000008,
.model_id = "Intel Core Processor (Broadwell, no TSX)",
},
{
@@ -1203,7 +1202,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_7_0_EBX_SMAP,
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT,
- .xlevel = 0x8000000A,
+ .xlevel = 0x80000008,
.model_id = "Intel Core Processor (Broadwell)",
},
{
@@ -1387,6 +1386,32 @@ void x86_cpu_compat_set_features(const char *cpu_model,
FeatureWord w,
}
}
+void x86_cpu_compat_set_level(const char *cpu_model, uint32_t level)
+{
+ X86CPUDefinition *def;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
+ def = &builtin_x86_defs[i];
+ if (!cpu_model || !strcmp(cpu_model, def->name)) {
+ def->level = level;
+ }
+ }
+}
+
+void x86_cpu_compat_set_xlevel(const char *cpu_model, uint32_t xlevel)
+{
+ X86CPUDefinition *def;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
+ def = &builtin_x86_defs[i];
+ if (!cpu_model || !strcmp(cpu_model, def->name)) {
+ def->xlevel = xlevel;
+ }
+ }
+}
+
static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
bool migratable_only);
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 603aaf0924e3..b1f16ee6195a 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1331,6 +1331,9 @@ void cpu_report_tpr_access(CPUX86State *env, TPRAccess
access);
void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
uint32_t feat_add, uint32_t feat_remove);
+void x86_cpu_compat_set_level(const char *cpu_model, uint32_t level);
+void x86_cpu_compat_set_xlevel(const char *cpu_model, uint32_t xlevel);
+
void x86_cpu_compat_kvm_no_autoenable(FeatureWord w, uint32_t features);
void x86_cpu_compat_kvm_no_autodisable(FeatureWord w, uint32_t features);
--
2.4.4
- [Qemu-devel] [PATCH v2] target-i386: emulate CPUID level of real hardware,
Radim Krčmář <=