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Re: [Qemu-devel] [PATCH pic32 v3 02/16] pic32: use LCG algorithm for gen
From: |
Aurelien Jarno |
Subject: |
Re: [Qemu-devel] [PATCH pic32 v3 02/16] pic32: use LCG algorithm for generated random index of TLBWR instruction |
Date: |
Mon, 6 Jul 2015 10:43:59 +0200 |
User-agent: |
Mutt/1.5.23 (2014-03-12) |
On 2015-07-05 23:14, Serge Vakulenko wrote:
> The LFSR algorithm, used for generating random TLB indexes for TLBWR
> instruction,
> was inclined to produce a degenerate sequence in some cases.
> For example, for 16-entry TLB size and Wired=1, it gives: 15, 6, 7, 2,
> 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2, 7, 2...
> When replaced with LCG algorithm from ISO/IEC 9899 standard, the sequence
> looks much better, with about the same computational effort needed.
>
> Signed-off-by: Serge Vakulenko <address@hidden>
> ---
> hw/mips/cputimer.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/hw/mips/cputimer.c b/hw/mips/cputimer.c
> index 75917cf..58707ed 100644
> --- a/hw/mips/cputimer.c
> +++ b/hw/mips/cputimer.c
> @@ -28,13 +28,16 @@
> /* XXX: do not use a global */
> uint32_t cpu_mips_get_random (CPUMIPSState *env)
> {
> - static uint32_t lfsr = 1;
> + static uint32_t seed = 1;
> static uint32_t prev_idx = 0;
> uint32_t idx;
> /* Don't return same value twice, so get another value */
> do {
> - lfsr = (lfsr >> 1) ^ (-(lfsr & 1u) & 0xd0000001u);
> - idx = lfsr % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
> + /* Use a simple algorithm of Linear Congruential Generator
> + * from ISO/IEC 9899 standard. */
> + seed = 1103515245 * seed + 12345;
> + idx = (seed >> 16) % (env->tlb->nb_tlb - env->CP0_Wired) +
> + env->CP0_Wired;
> } while (idx == prev_idx);
> prev_idx = idx;
> return idx;
This is indeed better, it seems the generated values are also better in
the standard Linux case (16 entries, wired = 0).
Reviewed-by: Aurelien Jarno <address@hidden>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
address@hidden http://www.aurel32.net
- [Qemu-devel] [PATCH pic32 v3 00/16] add support for pic32 microcontrollers, Serge Vakulenko, 2015/07/06
- [Qemu-devel] [PATCH pic32 v3 01/16] pic32: make the CPU clock frequency configurable per platform, Serge Vakulenko, 2015/07/06
- [Qemu-devel] [PATCH pic32 v3 02/16] pic32: use LCG algorithm for generated random index of TLBWR instruction, Serge Vakulenko, 2015/07/06
- Re: [Qemu-devel] [PATCH pic32 v3 02/16] pic32: use LCG algorithm for generated random index of TLBWR instruction,
Aurelien Jarno <=
- [Qemu-devel] [PATCH pic32 v3 03/16] pic32: add support for external interrupt controller mode (EIC), Serge Vakulenko, 2015/07/06
- [Qemu-devel] [PATCH pic32 v3 04/16] pic32: add two MIPS processor variants: M4K and microAptivUP, Serge Vakulenko, 2015/07/06
- [Qemu-devel] [PATCH pic32 v3 05/16] pic32: add file pic32_peripherals.h, Serge Vakulenko, 2015/07/06
- [Qemu-devel] [PATCH pic32 v3 06/16] pic32: add file pic32mx.h, Serge Vakulenko, 2015/07/06
- [Qemu-devel] [PATCH pic32 v3 10/16] pic32: add file pic32_load_hex.c, Serge Vakulenko, 2015/07/06