Re: [Qemu-devel] [PATCH for-2.4] target-arm: Fix broken SCTLR_EL3 reset

[Edgar E. Iglesias]

On Mon, Jul 13, 2015 at 03:24:25PM +0100, Peter Maydell wrote:
> The SCTLR_EL3 cpreg definition was implicitly resetting the
> register state to 0, which is both wrong and clashes with
> the reset done via the SCTLR definition (since sctlr[3]
> is unioned with sctlr_s). This went unnoticed until recently,
> when an unrelated change (commit a903c449b41f105aa) happened to
> perturb the order of enumeration through the cpregs hashtable for
> reset such that the erroneous reset happened after the correct one
> rather than before it. Fix this by marking SCTLR_EL3 as an alias,
> so its reset is left up to the AArch32 view.
> 
> Signed-off-by: Peter Maydell <address@hidden>


Ouch! Thanks!

Reviewed-by: Edgar E. Iglesias <address@hidden>

Cheers,
Edgar

> ---
> This was causing Greg's trustzone testsuite to fail.
> 
>  target-arm/helper.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index b87afe7..01f0d0d 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2752,6 +2752,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
>        .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0,
>        .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
>      { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
> +      .type = ARM_CP_ALIAS, /* reset handled by AArch32 view */
>        .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
>        .access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
>        .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]) },
> -- 
> 1.9.1
> 
>