Re: [Qemu-devel] [PATCH 4/6] ARM: Cortex-M3/M4: on exception, set basic bits in exhandling registers

[Peter Maydell]

On 7 July 2015 at 19:25, Alex Zuepke <address@hidden> wrote:
>
> Signed-off-by: Alex Zuepke <address@hidden>
> ---
>  target-arm/helper.c |    7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 812204f..555bc5f 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -4541,6 +4541,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
>         one we're raising.  */
>      switch (cs->exception_index) {
>      case EXCP_UDEF:
> +        env->v7m.cfsr |= CFSR_UNDEFINSTR;

I think you can also get here for attempts to use the
(nonexistent on M3) coprocessor instructions. Those should
set CFSR_NOCP, not CFSR_UNDEFINSTR.

>          armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
>          return;
>      case EXCP_SWI:
> @@ -4549,9 +4550,9 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
>          return;
>      case EXCP_PREFETCH_ABORT:
>      case EXCP_DATA_ABORT:
> -        /* TODO: if we implemented the MPU registers, this is where we
> -         * should set the MMFAR, etc from exception.fsr and 
> exception.vaddress.
> -         */
> +        env->v7m.mmfar = env->exception.vaddress;
> +        env->v7m.cfsr |= CFSR_MMARVALID;

Similarly, this can happen for both an MPU fault and a
BusFault, and the set of registers you need to update is different.
If you can't get enough information out of the exception.fsr
to determine the difference, you'll need to capture it earlier
(where we do for the other exception.* fields).

> +        /* TODO: further decoding of exception.fsr */
>          armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
>          return;
>      case EXCP_BKPT:
> --
> 1.7.9.5
>

thanks
-- PMM