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[Qemu-devel] [PATCH 5/5] hw/intc/arm_gic: Actually set the active bits f
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 5/5] hw/intc/arm_gic: Actually set the active bits for active interrupts |
Date: |
Tue, 28 Jul 2015 14:22:28 +0100 |
Although we were correctly handling interrupts becoming active
and then inactive, we weren't actually exposing this to the guest
by setting the 'active' flag for the interrupt, so reads
of GICD_ICACTIVERn and GICD_ISACTIVERn would generally incorrectly
return zeroes. Correct this oversight.
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/arm_gic.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 427c221..dc5a44b 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -262,6 +262,7 @@ static void gic_activate_irq(GICState *s, int cpu, int irq)
}
s->running_priority[cpu] = prio;
+ GIC_SET_ACTIVE(irq, 1 << cpu);
}
static int gic_get_prio_from_apr_bits(GICState *s, int cpu)
@@ -536,6 +537,7 @@ void gic_complete_irq(GICState *s, int cpu, int irq,
MemTxAttrs attrs)
*/
gic_drop_prio(s, cpu, group);
+ GIC_CLEAR_ACTIVE(irq, cm);
gic_update(s);
}
--
1.9.1
- [Qemu-devel] [PATCH 0/5] arm_gic: Drop running_irq and last_active arrays, Peter Maydell, 2015/07/28
- [Qemu-devel] [PATCH 5/5] hw/intc/arm_gic: Actually set the active bits for active interrupts,
Peter Maydell <=
- [Qemu-devel] [PATCH 1/5] armv7m_nvic: Implement ICSR without using internal GIC state, Peter Maydell, 2015/07/28
- [Qemu-devel] [PATCH 2/5] hw/intc/arm_gic: Running priority is group priority, not full priority, Peter Maydell, 2015/07/28
- [Qemu-devel] [PATCH 3/5] hw/intc/arm_gic: Fix handling of GICC_APR<n>, GICC_NSAPR<n> registers, Peter Maydell, 2015/07/28
- [Qemu-devel] [PATCH 4/5] hw/intc/arm_gic: Drop running_irq and last_active arrays, Peter Maydell, 2015/07/28