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[Qemu-devel] [RFC 13/14] Enable negative icount values for QEMU.
From: |
Christopher Covington |
Subject: |
[Qemu-devel] [RFC 13/14] Enable negative icount values for QEMU. |
Date: |
Wed, 5 Aug 2015 12:51:22 -0400 |
The icount setting specifies how far to shift the instruction
count as a ratio of ns to tie system time to instruction count.
Allow a negative value (i.e. a right shift instead of a left shift)
to be used.
Written by Pat Galizia.
Signed-off-by: Christopher Covington <address@hidden>
---
cpus.c | 17 +++++++++++++----
target-arm/helper.c | 14 ++++++++++++++
2 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/cpus.c b/cpus.c
index 62d157a..1c92a85 100644
--- a/cpus.c
+++ b/cpus.c
@@ -110,6 +110,8 @@ static int64_t vm_clock_warp_start = -1;
static int icount_time_shift;
/* Arbitrarily pick 1MIPS as the minimum allowable speed. */
#define MAX_ICOUNT_SHIFT 10
+/* In cases where we have a negative icount shift, specify a lower bound. */
+#define MIN_ICOUNT_SHIFT -5
static QEMUTimer *icount_rt_timer;
static QEMUTimer *icount_vm_timer;
@@ -174,6 +176,8 @@ int64_t cpu_get_icount(void)
int64_t cpu_icount_to_ns(int64_t icount)
{
+ if (icount_time_shift < 0)
+ return icount >> (-icount_time_shift);
return icount << icount_time_shift;
}
@@ -271,6 +275,7 @@ static void icount_adjust(void)
int64_t cur_time;
int64_t cur_icount;
int64_t delta;
+ int64_t icount_shifted;
/* Protected by TimersState mutex. */
static int64_t last_delta;
@@ -287,8 +292,8 @@ static void icount_adjust(void)
delta = cur_icount - cur_time;
/* FIXME: This is a very crude algorithm, somewhat prone to oscillation.
*/
if (delta > 0
- && last_delta + ICOUNT_WOBBLE < delta * 2
- && icount_time_shift > 0) {
+ && last_delta + ICOUNT_WOBBLE < delta * 2
+ && icount_time_shift > MIN_ICOUNT_SHIFT) {
/* The guest is getting too far ahead. Slow time down. */
icount_time_shift--;
}
@@ -299,8 +304,10 @@ static void icount_adjust(void)
icount_time_shift++;
}
last_delta = delta;
- timers_state.qemu_icount_bias = cur_icount
- - (timers_state.qemu_icount <<
icount_time_shift);
+ icount_shifted = (icount_time_shift >= 0) ?
+ timers_state.qemu_icount << icount_time_shift :
+ timers_state.qemu_icount >> (-icount_time_shift);
+ timers_state.qemu_icount_bias = cur_icount - icount_shifted;
seqlock_write_unlock(&timers_state.vm_clock_seqlock);
}
@@ -321,6 +328,8 @@ static void icount_adjust_vm(void *opaque)
static int64_t qemu_icount_round(int64_t count)
{
+ if (icount_time_shift < 0)
+ return count;
return (count + (1 << icount_time_shift) - 1) >> icount_time_shift;
}
diff --git a/target-arm/helper.c b/target-arm/helper.c
index ae0a4ac..0436df5 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4345,6 +4345,11 @@ void context_check_pid(CPUARMState *env)
void update_instruction_count(CPUARMState *env)
{
+ CPUState *cpu = CPU(arm_env_get_cpu(env));
+ int prevIoState = cpu->can_do_io;
+ if (use_icount)
+ cpu->can_do_io = 1;
+
if (bbtrace_initialized()) {
/*
* If the bbv plugin is compiled in and enabled, we must account for
the
@@ -4368,15 +4373,24 @@ void update_instruction_count(CPUARMState *env)
pmevcntr_increment(env, PMU_COUNTER_TYPE_CYCLES, env->prof_ic);
env->prof_ic = 0;
}
+
+ if (use_icount)
+ cpu->can_do_io = prevIoState;
}
#else //!CONFIG_BBVEC
void update_instruction_count(CPUARMState *env)
{
+ CPUState *cpu = CPU(arm_env_get_cpu(env));
+ int prevIoState = cpu->can_do_io;
+ if (use_icount)
+ cpu->can_do_io = 1;
pmevcntr_increment(env, PMU_COUNTER_TYPE_INSTRUCTIONS, env->prof_ic);
pmevcntr_increment(env, PMU_COUNTER_TYPE_CYCLES, env->prof_ic);
env->prof_ic = 0;
+ if (use_icount)
+ cpu->can_do_io = prevIoState;
}
#endif //CONFIG_BBVEC
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
- Re: [Qemu-devel] [RFC 01/14] Make unknown semihosting calls non-fatal, (continued)
- [Qemu-devel] [RFC 03/14] Fix makefile, Christopher Covington, 2015/08/05
- [Qemu-devel] [RFC 04/14] Modify load exclusive/store exclusive to use physical addresses with the monitor, Christopher Covington, 2015/08/05
- [Qemu-devel] [RFC 02/14] Added semihosting support for A64 in full-system mode, Christopher Covington, 2015/08/05
- [Qemu-devel] [RFC 05/14] Fixed TLB invalidate ops., Christopher Covington, 2015/08/05
- [Qemu-devel] [RFC 12/14] bbvec: Detect mode changes after uncached_cpsr update, Christopher Covington, 2015/08/05
- [Qemu-devel] [RFC 10/14] bbvec: Move mode/PID change detection to register writes, Christopher Covington, 2015/08/05
- [Qemu-devel] [RFC 07/14] Add PMU to ARM virt platform, Christopher Covington, 2015/08/05
- [Qemu-devel] [RFC 08/14] Add instruction-counting infrastructure to target-arm, Christopher Covington, 2015/08/05
- [Qemu-devel] [RFC 13/14] Enable negative icount values for QEMU.,
Christopher Covington <=
- [Qemu-devel] [RFC 11/14] Print bbvec stats on 'magic' exceptions, Christopher Covington, 2015/08/05
- [Qemu-devel] [RFC 09/14] Implement remaining PMU functionality, Christopher Covington, 2015/08/05
- [Qemu-devel] [RFC 06/14] Added support for block profiling for AArch32 and Aarch64, Christopher Covington, 2015/08/05
- [Qemu-devel] [RFC 14/14] bbvec: Properly detect conditional thumb2 branching instructions, Christopher Covington, 2015/08/05
- Re: [Qemu-devel] RFC: ARM Semihosting, PMU, and BBV Changes, Peter Maydell, 2015/08/11