[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [RFC PATCH V7 15/19] arm: use tlb_flush*_all
From: |
fred . konrad |
Subject: |
[Qemu-devel] [RFC PATCH V7 15/19] arm: use tlb_flush*_all |
Date: |
Mon, 10 Aug 2015 17:27:13 +0200 |
From: KONRAD Frederic <address@hidden>
This just use the new mechanism to ensure that each VCPU thread flush its own
VCPU.
Signed-off-by: KONRAD Frederic <address@hidden>
---
target-arm/helper.c | 45 +++++++--------------------------------------
1 file changed, 7 insertions(+), 38 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 34b465c..9acd7e5 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -411,41 +411,25 @@ static void tlbimvaa_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *other_cs;
-
- CPU_FOREACH(other_cs) {
- tlb_flush(other_cs, 1);
- }
+ tlb_flush_all(1);
}
static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *other_cs;
-
- CPU_FOREACH(other_cs) {
- tlb_flush(other_cs, value == 0);
- }
+ tlb_flush_all(value == 0);
}
static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *other_cs;
-
- CPU_FOREACH(other_cs) {
- tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
- }
+ tlb_flush_page_all(value & TARGET_PAGE_MASK);
}
static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *other_cs;
-
- CPU_FOREACH(other_cs) {
- tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
- }
+ tlb_flush_page_all(value & TARGET_PAGE_MASK);
}
static const ARMCPRegInfo cp_reginfo[] = {
@@ -2281,34 +2265,19 @@ static void tlbi_aa64_asid_write(CPUARMState *env,
const ARMCPRegInfo *ri,
static void tlbi_aa64_va_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *other_cs;
- uint64_t pageaddr = sextract64(value << 12, 0, 56);
-
- CPU_FOREACH(other_cs) {
- tlb_flush_page(other_cs, pageaddr);
- }
+ tlb_flush_page_all(sextract64(value << 12, 0, 56));
}
static void tlbi_aa64_vaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *other_cs;
- uint64_t pageaddr = sextract64(value << 12, 0, 56);
-
- CPU_FOREACH(other_cs) {
- tlb_flush_page(other_cs, pageaddr);
- }
+ tlb_flush_page_all(sextract64(value << 12, 0, 56));
}
static void tlbi_aa64_asid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- CPUState *other_cs;
- int asid = extract64(value, 48, 16);
-
- CPU_FOREACH(other_cs) {
- tlb_flush(other_cs, asid == 0);
- }
+ tlb_flush_all(extract64(value, 48, 16) == 0);
}
static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)
--
1.9.0
- [Qemu-devel] [RFC PATCH V7 11/19] tcg: switch on multithread., (continued)
- [Qemu-devel] [RFC PATCH V7 11/19] tcg: switch on multithread., fred . konrad, 2015/08/10
- [Qemu-devel] [RFC PATCH V7 13/19] add a callback when tb_invalidate is called., fred . konrad, 2015/08/10
- [Qemu-devel] [RFC PATCH V7 10/19] cpu: remove exit_request global., fred . konrad, 2015/08/10
- [Qemu-devel] [RFC PATCH V7 12/19] Use atomic cmpxchg to atomically check the exclusive value in a STREX, fred . konrad, 2015/08/10
- [Qemu-devel] [RFC PATCH V7 14/19] cpu: introduce tlb_flush*_all., fred . konrad, 2015/08/10
- [Qemu-devel] [RFC PATCH V7 15/19] arm: use tlb_flush*_all,
fred . konrad <=
- [Qemu-devel] [RFC PATCH V7 18/19] mttcg: signal the associated cpu anyway., fred . konrad, 2015/08/10
- [Qemu-devel] [RFC PATCH V7 16/19] translate-all: introduces tb_flush_safe., fred . konrad, 2015/08/10
- [Qemu-devel] [RFC PATCH V7 17/19] translate-all: (wip) use tb_flush_safe when we can't alloc more tb., fred . konrad, 2015/08/10
- [Qemu-devel] [RFC PATCH V7 19/19] target-arm/psci.c: wake up sleeping CPUs (MTTCG), fred . konrad, 2015/08/10