Re: [Qemu-devel] [PATCH v8 1/5] Implement GIC-500 base class

[Pavel Fedin]

> > +#define GICV3_NCPU 64
> 
> What is imposing this NCPU limit?

 Currently qemu does not support Aff2 field. Can we have more than 64 CPUs only 
with Aff0 and Aff1?
 Well, if you really-really insist, i can just raise it to 128 and stop it 
finally. It's actually Shlomo's heritage, and i believe his SW emulation will 
decrease this down to 64 again. It can be changed at any moment, i don't see 
any serious obstacles for it. You ask this question for the 3rd time IIRC, and 
i answer the same thing for the 3rd time. Does this little #define really worth 
it?
 Shlomo, your word?

> > +    qemu_irq parent_irq[GICV3_NCPU];
> > +    qemu_irq parent_fiq[GICV3_NCPU];
> 
> We should be allocating memory for the right number of irqs
> and fiqs based on the number of actual CPUs, because we don't
> really want a compile-time arbitrary limit on NCPUs.

 These arrays are just placeholders, so we reserve the maximum possible space 
for them. When we initialize the actual objects, of course we use only 
'num_cpu' slots in each of the array.
 sizeof(qemu_irq) is rather small (IIRC it's a pointer accompanied by number). 
Does it worth g_malloc()ing them dynamically?

Kind regards,
Pavel Fedin
Expert Engineer
Samsung Electronics Research center Russia