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Re: [Qemu-devel] [PATCH for-2.5 01/30] m68k: define m680x0 CPUs and feat
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH for-2.5 01/30] m68k: define m680x0 CPUs and features |
Date: |
Tue, 11 Aug 2015 16:13:59 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.1.0 |
On 08/09/2015 01:13 PM, Laurent Vivier wrote:
> INSN(undef, 0000, 0000, CF_ISA_A);
> + INSN(undef, 0000, 0000, M68000);
> INSN(arith_im, 0080, fff8, CF_ISA_A);
> + INSN(arith_im, 0000, ff00, M68000);
> + INSN(undef, 00c0, ffc0, M68000);
> INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC);
> INSN(bitop_reg, 0100, f1c0, CF_ISA_A);
> + INSN(bitop_reg, 0100, f1c0, M68000);
> INSN(bitop_reg, 0140, f1c0, CF_ISA_A);
> + INSN(bitop_reg, 0140, f1c0, M68000);
There's a *lot* of repetition in here.
Can we also introduce a BASE() macro that's like INSN() except that it doesn't
bother checking m68k_feature? That way if both CF_ISA_A and M68000 are set, we
don't have to duplicate the entry.
r~
- Re: [Qemu-devel] [PATCH for-2.5 05/30] m68k: define operand sizes, (continued)
- [Qemu-devel] [PATCH for-2.5 12/30] m68k: Manage divw overflow, Laurent Vivier, 2015/08/09
- [Qemu-devel] [PATCH for-2.5 14/30] m68k: allow adda/suba to add/sub word, Laurent Vivier, 2015/08/09
- [Qemu-devel] [PATCH for-2.5 13/30] m68k: set Z and N on divu/muls overflow as a real 68040, Laurent Vivier, 2015/08/09
- [Qemu-devel] [PATCH for-2.5 07/30] m68k: allow to update flags with operation on words and bytes, Laurent Vivier, 2015/08/09
- [Qemu-devel] [PATCH for-2.5 01/30] m68k: define m680x0 CPUs and features, Laurent Vivier, 2015/08/09
- Re: [Qemu-devel] [PATCH for-2.5 01/30] m68k: define m680x0 CPUs and features,
Richard Henderson <=
- [Qemu-devel] [PATCH for-2.5 15/30] m68k: add more modes to movem, Laurent Vivier, 2015/08/09
- [Qemu-devel] [PATCH for-2.5 08/30] m68k: update CPU flags management, Laurent Vivier, 2015/08/09