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Re: [Qemu-devel] [PATCH for-2.5 20/30] m68k: add exg
From: |
Laurent Vivier |
Subject: |
Re: [Qemu-devel] [PATCH for-2.5 20/30] m68k: add exg |
Date: |
Thu, 13 Aug 2015 00:43:04 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.1.0 |
Le 12/08/2015 19:05, Richard Henderson a écrit :
> On 08/09/2015 01:13 PM, Laurent Vivier wrote:
>> Signed-off-by: Laurent Vivier <address@hidden>
>> ---
>> target-m68k/translate.c | 34 +++++++++++++++++++++++++++++++++-
>> 1 file changed, 33 insertions(+), 1 deletion(-)
>>
>> diff --git a/target-m68k/translate.c b/target-m68k/translate.c
>> index adf4521..b7d15e9 100644
>> --- a/target-m68k/translate.c
>> +++ b/target-m68k/translate.c
>> @@ -2035,10 +2035,42 @@ DISAS_INSN(and)
>> TCGv dest;
>> TCGv addr;
>> int opsize;
>> + int exg_mode;
>>
>> + dest = tcg_temp_new();
>> +
>> + /* exg */
>> +
>> + exg_mode = insn & 0x1f8;
>
> Likewise, surely we can decode EXG separately from AND, and avoid doing so for
> coldfire.
I agree for CMPM, not for EXG.
Let's have a look to instructions encoding :)
AND 1100dddooommmrrr
ddd data register number
ooo opmode, invalid: 011, 111
mmmrrr ea mode, if ooo = { 000, 001, 010} invalid: 001000 .. 001111
if ooo = { 100, 101, 110} invalid; 000000 .. 001111
EXG 1100xxx1oooooyyy
xxx register
ooooo valid: 01000, 01001, 10001
yyy register
So, EXG is an AND with
ooo 101, 110
mmm 000, 001
which are invalid combinations for AND.
IMHO, EXG looks like a wart on the AND and should be decoded like that...
I don't know how to add this easily in the table... except by adding 3
entries to decode 1 instruction. Is it acceptable ?
Laurent
- Re: [Qemu-devel] [PATCH for-2.5 08/30] m68k: update CPU flags management, (continued)
[Qemu-devel] [PATCH for-2.5 21/30] m68k: add bkpt, Laurent Vivier, 2015/08/09
[Qemu-devel] [PATCH for-2.5 19/30] m68k: add cmpm, Laurent Vivier, 2015/08/09
[Qemu-devel] [PATCH for-2.5 25/30] m68k: add abcd, sbcd, nbcd instructions, Laurent Vivier, 2015/08/09
[Qemu-devel] [PATCH for-2.5 24/30] m68k: add DBcc and Scc (memory operand), Laurent Vivier, 2015/08/09