Re: [Qemu-devel] [PATCH 0/6] flush TLBs for one MMUidx only, missing AArch64 TLB ops

[Edgar E. Iglesias]

On Fri, Aug 07, 2015 at 01:33:24PM +0100, Peter Maydell wrote:
> This series does three things:

Hi,

Looks good to me!

Reviewed-by: Edgar E. Iglesias <address@hidden>

Cheers,
Edgar


> 
> (1) implement the "flush the TLB only for a specified MMU index"
> functionality that we talked about when we added all the new
> MMU index values for ARM for EL2 and EL3
> 
> (2) use that to restrict the AArch64 TLB maintenance operations
> to only the MMU indexes they need to touch
> 
> (3) add all the missing EL2 and EL3 related TLB operations for
> AArch64
> 
> I did a quick performance test by running hackbench. Measuring
> suggests that performance is improved by between half and one
> percent, which isn't fantastic but then I don't know how much
> of hackbench's runtime is bottlenecked by TLB flushes. I would
> expect that a workload that actually used EL2 and EL3 will
> benefit by not having the EL2 and EL3 flushes taking out the
> EL1&0 TLB too.
> 
> Disclaimer: the EL2 and EL3 parts of this code are untested
> because we haven't completely implemented those for AArch64 yet.
> 
> 
> Peter Maydell (6):
>   cputlb: Add functions for flushing TLB for a single MMU index
>   target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order
>   target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must
>     touch
>   target-arm: Implement missing EL2 TLBI operations
>   target-arm: Implement missing EL3 TLB invalidate operations
>   target-arm: Implement AArch64 TLBI operations on IPAs
> 
>  cputlb.c                |  81 ++++++++++++
>  include/exec/exec-all.h |  47 +++++++
>  target-arm/helper.c     | 329 
> +++++++++++++++++++++++++++++++++++++++++-------
>  3 files changed, 412 insertions(+), 45 deletions(-)
> 
> -- 
> 1.9.1
>