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[Qemu-devel] [PATCH 06/11] target-m68k: Introduce DisasCompare
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 06/11] target-m68k: Introduce DisasCompare |
Date: |
Fri, 14 Aug 2015 07:59:21 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target-m68k/translate.c | 82 ++++++++++++++++++++++++++++++++++++-------------
1 file changed, 60 insertions(+), 22 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index b0cb39d..ce48e2a 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -781,8 +781,15 @@ static TCGv gen_ea(CPUM68KState *env, DisasContext *s,
uint16_t insn,
return NULL_QREG;
}
-/* This generates a conditional branch, clobbering all temporaries. */
-static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
+typedef struct {
+ TCGCond tcond;
+ bool g1;
+ bool g2;
+ TCGv v1;
+ TCGv v2;
+} DisasCompare;
+
+static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond)
{
TCGv tmp, tmp2;
TCGCond tcond;
@@ -790,60 +797,91 @@ static void gen_jmpcc(DisasContext *s, int cond, TCGLabel
*l1)
/* TODO: Optimize compare/branch pairs rather than always flushing
flag state to CC_OP_FLAGS. */
gen_flush_flags(s);
+
+ c->g1 = 1;
+ c->g2 = 0;
+ c->v2 = tcg_const_i32(0);
+
switch (cond) {
case 0: /* T */
- tcg_gen_br(l1);
- return;
case 1: /* F */
- return;
+ c->v1 = c->v2;
+ tcond = TCG_COND_NEVER;
+ break;
case 2: /* HI (!C && !Z) -> !(C || Z)*/
case 3: /* LS (C || Z) */
- tmp = tcg_temp_new();
- tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, QREG_CC_Z, 0);
+ c->v1 = tmp = tcg_temp_new();
+ c->g1 = 0;
+ tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
tcg_gen_or_i32(tmp, tmp, QREG_CC_C);
- tcond = (cond & 1 ? TCG_COND_NE: TCG_COND_EQ);
+ tcond = TCG_COND_NE;
break;
case 4: /* CC (!C) */
case 5: /* CS (C) */
- tmp = QREG_CC_C;
- tcond = (cond & 1 ? TCG_COND_NE : TCG_COND_EQ);
+ c->v1 = QREG_CC_C;
+ tcond = TCG_COND_NE;
break;
case 6: /* NE (!Z) */
case 7: /* EQ (Z) */
- tmp = QREG_CC_Z;
- tcond = (cond & 1 ? TCG_COND_EQ : TCG_COND_NE);
+ c->v1 = QREG_CC_Z;
+ tcond = TCG_COND_EQ;
break;
case 8: /* VC (!V) */
case 9: /* VS (V) */
- tmp = QREG_CC_V;
- tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE);
+ c->v1 = QREG_CC_V;
+ tcond = TCG_COND_LT;
break;
case 10: /* PL (!N) */
case 11: /* MI (N) */
- tmp = QREG_CC_N;
- tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE);
+ c->v1 = QREG_CC_N;
+ tcond = TCG_COND_LT;
break;
case 12: /* GE (!(N ^ V)) */
case 13: /* LT (N ^ V) */
- tmp = tcg_temp_new();
+ c->v1 = tmp = tcg_temp_new();
+ c->g1 = 0;
tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V);
- tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE);
+ tcond = TCG_COND_LT;
break;
case 14: /* GT (!(Z || (N ^ V))) */
case 15: /* LE (Z || (N ^ V)) */
- tmp = tcg_temp_new();
- tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, QREG_CC_Z, 0);
+ c->v1 = tmp = tcg_temp_new();
+ c->g1 = 0;
+ tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
tcg_gen_neg_i32(tmp, tmp);
tmp2 = tcg_temp_new();
tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V);
tcg_gen_or_i32(tmp, tmp, tmp2);
- tcond = (cond & 1 ? TCG_COND_LT : TCG_COND_GE);
+ tcg_temp_free(tmp2);
+ tcond = TCG_COND_LT;
break;
default:
/* Should ever happen. */
abort();
}
- tcg_gen_brcondi_i32(tcond, tmp, 0, l1);
+ if ((cond & 1) == 0) {
+ tcond = tcg_invert_cond(tcond);
+ }
+ c->tcond = tcond;
+}
+
+static void free_cond(DisasCompare *c)
+{
+ if (!c->g1) {
+ tcg_temp_free(c->v1);
+ }
+ if (!c->g2) {
+ tcg_temp_free(c->v2);
+ }
+}
+
+static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
+{
+ DisasCompare c;
+
+ gen_cc_cond(&c, s, cond);
+ tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
+ free_cond(&c);
}
DISAS_INSN(scc)
--
2.4.3
- [Qemu-devel] [PATCH 00/11] Proposed format for m68k flags, Richard Henderson, 2015/08/14
- [Qemu-devel] [PATCH 01/11] target-m68k: Print flags properly, Richard Henderson, 2015/08/14
- [Qemu-devel] [PATCH 02/11] target-m68k: Some fixes to SR and flags management, Richard Henderson, 2015/08/14
- [Qemu-devel] [PATCH 03/11] target-m68k: Remove incorrect clearing of cc_x, Richard Henderson, 2015/08/14
- [Qemu-devel] [PATCH 04/11] target-m68k: Replace helper_xflag_lt with setcond, Richard Henderson, 2015/08/14
- [Qemu-devel] [PATCH 07/11] target-m68k: Use setcond for scc, Richard Henderson, 2015/08/14
- [Qemu-devel] [PATCH 08/11] target-m68k: Optimize some comparisons, Richard Henderson, 2015/08/14
- [Qemu-devel] [PATCH 09/11] target-m68k: Optimize gen_flush_flags, Richard Henderson, 2015/08/14
- [Qemu-devel] [PATCH 10/11] target-m68k: Inline shifts, Richard Henderson, 2015/08/14
- [Qemu-devel] [PATCH 06/11] target-m68k: Introduce DisasCompare,
Richard Henderson <=
- [Qemu-devel] [PATCH 11/11] target-m68k: Inline addx, subx, negx, Richard Henderson, 2015/08/14
- [Qemu-devel] [PATCH 05/11] target-m68k: Reorg flags handling, Richard Henderson, 2015/08/14
- Re: [Qemu-devel] [PATCH 00/11] Proposed format for m68k flags, Laurent Vivier, 2015/08/14