Re: [Qemu-devel] [PATCH 03/17] target-openrisc: Invert the decoding in dec_calc

[Bastian Koppelmann]

On 09/03/2015 02:17 AM, Richard Henderson wrote:
> Decoding the opcodes in the right order reduces by 100+ lines.
> Also, it happens to put the opcodes in the same order as Chapter 17.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>   target-openrisc/translate.c | 300 ++++++++++++++------------------------------
>   1 file changed, 94 insertions(+), 206 deletions(-)
>
> diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
> index 9a8f886..c9e3198 100644
> --- a/target-openrisc/translate.c
> +++ b/target-openrisc/translate.c
> @@ -419,267 +419,155 @@ static void dec_calc(DisasContext *dc, uint32_t insn)
>       rb = extract32(insn, 11, 5);
>       rd = extract32(insn, 21, 5);
>   
> -    switch (op0) {

I think it's worth while to group all instructions with op0 = 0 into a 
separate decoding function.

> -
> -    case 0x000c:
> -        switch (op1) {
> -        case 0x00:
> +        case 0xc:
>               switch (op2) {
> -            case 0x00:    /* l.exths */
> +            case 0: /* l.exths */
>                   LOG_DIS("l.exths r%d, r%d\n", rd, ra);
>                   tcg_gen_ext16s_tl(cpu_R[rd], cpu_R[ra]);
Nitpick: l.exths comes before l.add in chapter 17 of my manual [1]

However those are mostly minor issues, so
Reviewed-by: Bastian Koppelmann <address@hidden>

Cheers,
Bastian

[1] 
https://github.com/openrisc/doc/blob/master/openrisc-arch-1.1-rev0.pdf?raw=true