[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH 12/17] target-openrisc: Enable m[tf]spr from use
|
From: |
Richard Henderson |
|
Subject: |
Re: [Qemu-devel] [PATCH 12/17] target-openrisc: Enable m[tf]spr from user mode |
|
Date: |
Sun, 06 Sep 2015 13:36:39 -0700 |
On Sep 5, 2015 14:35, Bastian Koppelmann <address@hidden> wrote:
> IIRC a lot of the registers are supervisor only, e.g. VR, NPC or SR and
> the manual is fairly clear about that. User mode cpu ought not to read
> these registers unconditionally.
When I last discussed this on the openrisc list, back in March, there was no
real specification for user mode, and what bits are or should be accessible.
Looking at
http://opencores.org/or1k/Architecture_Specification
today, that still seems to be the case.
In the meantime, dropping the privilege check makes linux-user GCC tests work
better.
r~
- [Qemu-devel] [PATCH 09/17] target-openrisc: Implement ff1 and fl1 for 64-bit, (continued)
- [Qemu-devel] [PATCH 09/17] target-openrisc: Implement ff1 and fl1 for 64-bit, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH 07/17] target-openrisc: Keep SR_CY and SR_OV in a separate variables, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH 13/17] target-openrisc: Enable trap, csync, msync, psync for user mode, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH 10/17] target-openrisc: Represent MACHI:MACLO as a single unit, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH 12/17] target-openrisc: Enable m[tf]spr from user mode, Richard Henderson, 2015/09/02
[Qemu-devel] [PATCH 11/17] target-openrisc: Rationalize immediate extraction, Richard Henderson, 2015/09/02
[Qemu-devel] [PATCH 15/17] target-openrisc: Fix madd, Richard Henderson, 2015/09/02
[Qemu-devel] [PATCH 14/17] target-openrisc: Implement muld, muldu, macu, msbu, Richard Henderson, 2015/09/02
[Qemu-devel] [PATCH 17/17] target-openrisc: Implement lwa, swa, Richard Henderson, 2015/09/02