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Re: [Qemu-devel] [PATCH v2 11/11] target-arm: Use tcg_gen_extrh_i64_i32
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v2 11/11] target-arm: Use tcg_gen_extrh_i64_i32 |
Date: |
Mon, 7 Sep 2015 19:11:42 +0100 |
On 2 September 2015 at 18:57, Richard Henderson <address@hidden> wrote:
> Usually, eliminate an operation from the translator by combining
> a shift with an extract.
>
> In the case of gen_set_NZ64, we don't need a boolean value for cpu_ZF,
> merely a non-zero value. Given that we can extract both halves of a
> 64-bit input in one call, this simplifies the code.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
Reviewed-by: Peter Maydell <address@hidden>
thanks
-- PMM
- Re: [Qemu-devel] [PATCH v2 05/11] target-arm: Implement ccmp branchless, (continued)
- [Qemu-devel] [PATCH v2 06/11] target-arm: Implement fcsel with movcond, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v2 07/11] target-arm: Recognize SXTB, SXTH, SXTW, ASR, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v2 09/11] target-arm: Eliminate unnecessary zero-extend in disas_bitfield, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v2 08/11] target-arm: Recognize UXTB, UXTH, LSR, LSL, Richard Henderson, 2015/09/02
- [Qemu-devel] [PATCH v2 11/11] target-arm: Use tcg_gen_extrh_i64_i32, Richard Henderson, 2015/09/02
- Re: [Qemu-devel] [PATCH v2 11/11] target-arm: Use tcg_gen_extrh_i64_i32,
Peter Maydell <=
- [Qemu-devel] [PATCH v2 10/11] target-arm: Recognize ROR, Richard Henderson, 2015/09/02