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[Qemu-devel] [PULL 02/20] hw/intc/arm_gic: Running priority is group pri
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 02/20] hw/intc/arm_gic: Running priority is group priority, not full priority |
Date: |
Tue, 8 Sep 2015 17:51:14 +0100 |
Priority values for the GIC are divided into a "group priority"
and a "subpriority" (with the division being determined by the
binary point register). The running priority is only determined
by the group priority of the active interrupts, not the
subpriority. In particular, this means that there can't be more
than one active interrupt at any particular group priority.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
---
hw/intc/arm_gic.c | 28 +++++++++++++++++++++++++++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index a8c5d19..1b8e839 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -219,13 +219,39 @@ static uint16_t gic_get_current_pending_irq(GICState *s,
int cpu,
return pending_irq;
}
+static int gic_get_group_priority(GICState *s, int cpu, int irq)
+{
+ /* Return the group priority of the specified interrupt
+ * (which is the top bits of its priority, with the number
+ * of bits masked determined by the applicable binary point register).
+ */
+ int bpr;
+ uint32_t mask;
+
+ if (gic_has_groups(s) &&
+ !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) &&
+ GIC_TEST_GROUP(irq, (1 << cpu))) {
+ bpr = s->abpr[cpu];
+ } else {
+ bpr = s->bpr[cpu];
+ }
+
+ /* a BPR of 0 means the group priority bits are [7:1];
+ * a BPR of 1 means they are [7:2], and so on down to
+ * a BPR of 7 meaning no group priority bits at all.
+ */
+ mask = ~0U << ((bpr & 7) + 1);
+
+ return GIC_GET_PRIORITY(irq, cpu) & mask;
+}
+
static void gic_set_running_irq(GICState *s, int cpu, int irq)
{
s->running_irq[cpu] = irq;
if (irq == 1023) {
s->running_priority[cpu] = 0x100;
} else {
- s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu);
+ s->running_priority[cpu] = gic_get_group_priority(s, cpu, irq);
}
gic_update(s);
}
--
1.9.1
- [Qemu-devel] [PULL 06/20] qom: Add recursive version of object_child_for_each, (continued)
- [Qemu-devel] [PULL 06/20] qom: Add recursive version of object_child_for_each, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 05/20] hw/intc/arm_gic: Actually set the active bits for active interrupts, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 01/20] armv7m_nvic: Implement ICSR without using internal GIC state, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 08/20] hw/intc/arm_gic_common: Configure IRQs as NS if doing direct NS kernel boot, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 04/20] hw/intc/arm_gic: Drop running_irq and last_active arrays, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 12/20] target-arm: Fix default_exception_el() function for the case when EL3 is not supported, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 07/20] hw/arm: new interface for devices which need to behave differently for kernel boot, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 17/20] ahci: Separate the AHCI state structure into the header, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 10/20] hw/arm/virt: Default to not providing TrustZone support, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 09/20] hw/cpu/{a15mpcore, a9mpcore}: enable TrustZone in GIC if it is enabled in CPUs, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 02/20] hw/intc/arm_gic: Running priority is group priority, not full priority,
Peter Maydell <=
- [Qemu-devel] [PULL 03/20] hw/intc/arm_gic: Fix handling of GICC_APR<n>, GICC_NSAPR<n> registers, Peter Maydell, 2015/09/08
- Re: [Qemu-devel] [PULL 00/20] target-arm queue, Peter Maydell, 2015/09/08