Re: [Qemu-devel] [Qemu-ppc] target-ppc: Fix SRR0 when taking unaligned exceptions

[Benjamin Herrenschmidt]

On Thu, 2015-07-02 at 14:44 +1000, Anton Blanchard wrote:
> We are setting SRR0 to the instruction before the one causing the
> unaligned exception. A quick testcase:
> 
 ../..

> p_helper.c b/target-ppc/excp_helper.c
> index b803475..4250106 100644
> --- a/target-ppc/excp_helper.c
> +++ b/target-ppc/excp_helper.c
> @@ -200,7 +200,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu,
> int excp_model, int excp)
>          /* Get rS/rD and rA from faulting opcode */
>          env->spr[SPR_DSISR] |= (cpu_ldl_code(env, (env->nip - 4))
>                                  & 0x03FF0000) >> 16;.

You need to also fix the above to use env->nip instead of env->nip - 4
when generating DSISR

> -        goto store_current;
> +        goto store_next;
>      case POWERPC_EXCP_PROGRAM:   /* Program exception               
>          */
>          switch (env->error_code & ~0xF) {
>          case POWERPC_EXCP_FP: