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[Qemu-devel] [PATCH v3 07/11] target-arm: Recognize SXTB, SXTH, SXTW, AS
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 07/11] target-arm: Recognize SXTB, SXTH, SXTW, ASR |
Date: |
Thu, 10 Sep 2015 11:18:19 -0700 |
These are all special case aliases of SBFM.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-arm/translate-a64.c | 24 +++++++++++++++++++++++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index bb0d752..0572635 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -3017,7 +3017,28 @@ static void disas_bitfield(DisasContext *s, uint32_t
insn)
tcg_rd = cpu_reg(s, rd);
tcg_tmp = read_cpu_reg(s, rn, sf);
- /* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */
+ /* Recognize the common aliases. */
+ if (opc == 0) { /* SBFM */
+ if (ri == 0) {
+ if (si == 7) { /* SXTB */
+ tcg_gen_ext8s_i64(tcg_rd, tcg_tmp);
+ goto done;
+ } else if (si == 15) { /* SXTH */
+ tcg_gen_ext16s_i64(tcg_rd, tcg_tmp);
+ goto done;
+ } else if (si == 31) { /* SXTW */
+ tcg_gen_ext32s_i64(tcg_rd, tcg_tmp);
+ goto done;
+ }
+ }
+ if (si == 63 || (si == 31 && ri <= si)) { /* ASR */
+ if (si == 31) {
+ tcg_gen_ext32s_i64(tcg_tmp, tcg_tmp);
+ }
+ tcg_gen_sari_i64(tcg_rd, tcg_tmp, ri);
+ goto done;
+ }
+ }
if (opc != 1) { /* SBFM or UBFM */
tcg_gen_movi_i64(tcg_rd, 0);
@@ -3042,6 +3063,7 @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
tcg_gen_sari_i64(tcg_rd, tcg_rd, 64 - (pos + len));
}
+ done:
if (!sf) { /* zero extend final result */
tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
}
--
2.4.3
- [Qemu-devel] [PATCH v3 00/11] target-arm improvments for aarch64, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 03/11] target-arm: Handle always condition codes within arm_test_cc, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 02/11] target-arm: Introduce DisasCompare, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 01/11] target-arm: Share all common TCG temporaries, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 04/11] target-arm: Use setcond and movcond for csel, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 07/11] target-arm: Recognize SXTB, SXTH, SXTW, ASR,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 08/11] target-arm: Recognize UXTB, UXTH, LSR, LSL, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 05/11] target-arm: Implement ccmp branchless, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 09/11] target-arm: Eliminate unnecessary zero-extend in disas_bitfield, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 11/11] target-arm: Use tcg_gen_extrh_i64_i32, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 06/11] target-arm: Implement fcsel with movcond, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 10/11] target-arm: Recognize ROR, Richard Henderson, 2015/09/10
- Re: [Qemu-devel] [PATCH v3 00/11] target-arm improvments for aarch64, Peter Maydell, 2015/09/11