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[Qemu-devel] [PULL 02/10] target-mips: remove wrong checks for recip.fmt
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 02/10] target-mips: remove wrong checks for recip.fmt and rsqrt.fmt |
Date: |
Fri, 18 Sep 2015 12:25:27 +0100 |
From: Petar Jovanovic <address@hidden>
Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither
they require any particular mode for its FPU. This patch removes the checks
that may break a program that uses these instructions.
Signed-off-by: Petar Jovanovic <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/translate.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 2f1e724..fadef9e 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -9290,7 +9290,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode
op1,
opn = "movn.s";
break;
case OPC_RECIP_S:
- check_cop1x(ctx);
{
TCGv_i32 fp0 = tcg_temp_new_i32();
@@ -9302,7 +9301,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode
op1,
opn = "recip.s";
break;
case OPC_RSQRT_S:
- check_cop1x(ctx);
{
TCGv_i32 fp0 = tcg_temp_new_i32();
@@ -9835,7 +9833,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode
op1,
opn = "movn.d";
break;
case OPC_RECIP_D:
- check_cp1_64bitmode(ctx);
+ check_cp1_registers(ctx, fs | fd);
{
TCGv_i64 fp0 = tcg_temp_new_i64();
@@ -9847,7 +9845,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode
op1,
opn = "recip.d";
break;
case OPC_RSQRT_D:
- check_cp1_64bitmode(ctx);
+ check_cp1_registers(ctx, fs | fd);
{
TCGv_i64 fp0 = tcg_temp_new_i64();
--
2.1.0
- [Qemu-devel] [PULL 00/10] target-mips queue, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 03/10] target-mips: Fix RDHWR on CP0.Count, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 05/10] target-mips: get rid of MIPS_DEBUG_SIGN_EXTENSIONS, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 07/10] target-mips: fix corner case in TLBWR causing QEMU to hang, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 08/10] target-mips: add missing restriction in DAUI instruction, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 09/10] target-mips: correct MTC0 instruction on MIPS64, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 10/10] target-mips: improve exception handling, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 02/10] target-mips: remove wrong checks for recip.fmt and rsqrt.fmt,
Leon Alrae <=
- [Qemu-devel] [PULL 06/10] pic32: use LCG algorithm for generated random index of TLBWR instruction, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 01/10] target-mips: Use tcg_gen_extrh_i64_i32, Leon Alrae, 2015/09/18
- [Qemu-devel] [PULL 04/10] target-mips: get rid of MIPS_DEBUG, Leon Alrae, 2015/09/18
- Re: [Qemu-devel] [PULL 00/10] target-mips queue, Peter Maydell, 2015/09/18