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[Qemu-devel] [PATCH] target-tilegx: Implement v*add and v*sub instructio
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From: |
gang . chen . 5i5j |
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Subject: |
[Qemu-devel] [PATCH] target-tilegx: Implement v*add and v*sub instructions |
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Date: |
Sat, 19 Sep 2015 08:03:26 +0800 |
From: Chen Gang <address@hidden>
Only according to helper_v1shrs.
Signed-off-by: Chen Gang <address@hidden>
---
target-tilegx/helper.h | 8 +++++
target-tilegx/simd_helper.c | 77 +++++++++++++++++++++++++++++++++++++++++++++
target-tilegx/translate.c | 26 +++++++++++++--
3 files changed, 109 insertions(+), 2 deletions(-)
diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
index 15093973..c366984 100644
--- a/target-tilegx/helper.h
+++ b/target-tilegx/helper.h
@@ -5,12 +5,20 @@ DEF_HELPER_FLAGS_1(pcnt, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(revbits, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v1add, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shru, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v1sub, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+
+DEF_HELPER_FLAGS_2(v2add, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v2shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v2shru, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v2shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v2sub, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+
+DEF_HELPER_FLAGS_2(v4add, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v4shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v4shru, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v4shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v4sub, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target-tilegx/simd_helper.c b/target-tilegx/simd_helper.c
index 6546337..ec589fe 100644
--- a/target-tilegx/simd_helper.c
+++ b/target-tilegx/simd_helper.c
@@ -22,6 +22,83 @@
#include "qemu-common.h"
#include "exec/helper-proto.h"
+uint64_t helper_v1add(uint64_t a, uint64_t b)
+{
+ uint64_t r = 0;
+ int i;
+
+ for (i = 0; i < 64; i += 8) {
+ int64_t ae = (int8_t)(a >> i);
+ int64_t be = (int8_t)(b >> i);
+ r |= ((ae + be) & 0xff) << i;
+ }
+ return r;
+}
+
+uint64_t helper_v2add(uint64_t a, uint64_t b)
+{
+ uint64_t r = 0;
+ int i;
+
+ for (i = 0; i < 64; i += 16) {
+ int64_t ae = (int16_t)(a >> i);
+ int64_t be = (int16_t)(b >> i);
+ r |= ((ae + be) & 0xffff) << i;
+ }
+ return r;
+}
+
+uint64_t helper_v4add(uint64_t a, uint64_t b)
+{
+ uint64_t r = 0;
+ int i;
+
+ for (i = 0; i < 64; i += 32) {
+ int64_t ae = (int32_t)(a >> i);
+ int64_t be = (int32_t)(b >> i);
+ r |= ((ae + be) & 0xffffffff) << i;
+ }
+ return r;
+}
+
+uint64_t helper_v1sub(uint64_t a, uint64_t b)
+{
+ uint64_t r = 0;
+ int i;
+
+ for (i = 0; i < 64; i += 8) {
+ int64_t ae = (int8_t)(a >> i);
+ int64_t be = (int8_t)(b >> i);
+ r |= ((ae - be) & 0xff) << i;
+ }
+ return r;
+}
+
+uint64_t helper_v2sub(uint64_t a, uint64_t b)
+{
+ uint64_t r = 0;
+ int i;
+
+ for (i = 0; i < 64; i += 16) {
+ int64_t ae = (int16_t)(a >> i);
+ int64_t be = (int16_t)(b >> i);
+ r |= ((ae - be) & 0xffff) << i;
+ }
+ return r;
+}
+
+uint64_t helper_v4sub(uint64_t a, uint64_t b)
+{
+ uint64_t r = 0;
+ int i;
+
+ for (i = 0; i < 64; i += 32) {
+ int64_t ae = (int32_t)(a >> i);
+ int64_t be = (int32_t)(b >> i);
+ r |= ((ae - be) & 0xffffffff) << i;
+ }
+ return r;
+}
uint64_t helper_v1shl(uint64_t a, uint64_t b)
{
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index c8247ac..2246243 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -1024,8 +1024,12 @@ static TileExcp gen_rrr_opcode(DisasContext *dc,
unsigned opext,
break;
case OE_RRR(V1ADDUC, 0, X0):
case OE_RRR(V1ADDUC, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V1ADD, 0, X0):
case OE_RRR(V1ADD, 0, X1):
+ gen_helper_v1add(tdest, tsrca, tsrcb);
+ mnemonic = "v1add";
+ break;
case OE_RRR(V1ADIFFU, 0, X0):
case OE_RRR(V1AVGU, 0, X0):
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
@@ -1095,12 +1099,20 @@ static TileExcp gen_rrr_opcode(DisasContext *dc,
unsigned opext,
break;
case OE_RRR(V1SUBUC, 0, X0):
case OE_RRR(V1SUBUC, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V1SUB, 0, X0):
case OE_RRR(V1SUB, 0, X1):
+ gen_helper_v1sub(tdest, tsrca, tsrcb);
+ mnemonic = "v1sub";
+ break;
case OE_RRR(V2ADDSC, 0, X0):
case OE_RRR(V2ADDSC, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V2ADD, 0, X0):
case OE_RRR(V2ADD, 0, X1):
+ gen_helper_v2add(tdest, tsrca, tsrcb);
+ mnemonic = "v2add";
+ break;
case OE_RRR(V2ADIFFS, 0, X0):
case OE_RRR(V2AVGS, 0, X0):
case OE_RRR(V2CMPEQ, 0, X0):
@@ -1162,13 +1174,20 @@ static TileExcp gen_rrr_opcode(DisasContext *dc,
unsigned opext,
break;
case OE_RRR(V2SUBSC, 0, X0):
case OE_RRR(V2SUBSC, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V2SUB, 0, X0):
case OE_RRR(V2SUB, 0, X1):
+ gen_helper_v2sub(tdest, tsrca, tsrcb);
+ mnemonic = "v2sub";
+ break;
case OE_RRR(V4ADDSC, 0, X0):
case OE_RRR(V4ADDSC, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V4ADD, 0, X0):
case OE_RRR(V4ADD, 0, X1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ gen_helper_v4add(tdest, tsrca, tsrcb);
+ mnemonic = "v4add";
+ break;
case OE_RRR(V4INT_H, 0, X0):
case OE_RRR(V4INT_H, 0, X1):
tcg_gen_shri_tl(tdest, tsrcb, 32);
@@ -1202,9 +1221,12 @@ static TileExcp gen_rrr_opcode(DisasContext *dc,
unsigned opext,
break;
case OE_RRR(V4SUBSC, 0, X0):
case OE_RRR(V4SUBSC, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V4SUB, 0, X0):
case OE_RRR(V4SUB, 0, X1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ gen_helper_v2sub(tdest, tsrca, tsrcb);
+ mnemonic = "v2sub";
+ break;
case OE_RRR(XOR, 0, X0):
case OE_RRR(XOR, 0, X1):
case OE_RRR(XOR, 5, Y0):
--
1.9.3
- [Qemu-devel] [PATCH] target-tilegx: Implement v*add and v*sub instructions,
gang . chen . 5i5j <=