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[Qemu-devel] [RFC v5 4/6] target-arm: Create new runtime helpers for exc
From: |
Alvise Rigo |
Subject: |
[Qemu-devel] [RFC v5 4/6] target-arm: Create new runtime helpers for excl accesses |
Date: |
Thu, 24 Sep 2015 10:32:44 +0200 |
Introduce a set of new runtime helpers do handle exclusive instructions.
This helpers are used as hooks to call the respective LL/SC helpers in
softmmu_llsc_template.h from TCG code.
Suggested-by: Jani Kokkonen <address@hidden>
Suggested-by: Claudio Fontana <address@hidden>
Signed-off-by: Alvise Rigo <address@hidden>
---
target-arm/helper.h | 10 ++++++
target-arm/op_helper.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 104 insertions(+)
diff --git a/target-arm/helper.h b/target-arm/helper.h
index 827b33d..8e7a7c2 100644
--- a/target-arm/helper.h
+++ b/target-arm/helper.h
@@ -530,6 +530,16 @@ DEF_HELPER_2(dc_zva, void, env, i64)
DEF_HELPER_FLAGS_2(neon_pmull_64_lo, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(neon_pmull_64_hi, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_3(ldlink_aa32_i8, i32, env, i32, i32)
+DEF_HELPER_3(ldlink_aa32_i16, i32, env, i32, i32)
+DEF_HELPER_3(ldlink_aa32_i32, i32, env, i32, i32)
+DEF_HELPER_3(ldlink_aa32_i64, i64, env, i32, i32)
+
+DEF_HELPER_4(stcond_aa32_i8, i32, env, i32, i32, i32)
+DEF_HELPER_4(stcond_aa32_i16, i32, env, i32, i32, i32)
+DEF_HELPER_4(stcond_aa32_i32, i32, env, i32, i32, i32)
+DEF_HELPER_4(stcond_aa32_i64, i32, env, i32, i64, i32)
+
#ifdef TARGET_AARCH64
#include "helper-a64.h"
#endif
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 663c05d..d832ba8 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -969,3 +969,97 @@ uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x,
uint32_t i)
return ((uint32_t)x >> shift) | (x << (32 - shift));
}
}
+
+/* LoadLink helpers, only unsigned. */
+static void * const qemu_ldex_helpers[16] = {
+ [MO_UB] = helper_ret_ldlinkub_mmu,
+
+ [MO_LEUW] = helper_le_ldlinkuw_mmu,
+ [MO_LEUL] = helper_le_ldlinkul_mmu,
+ [MO_LEQ] = helper_le_ldlinkq_mmu,
+
+ [MO_BEUW] = helper_be_ldlinkuw_mmu,
+ [MO_BEUL] = helper_be_ldlinkul_mmu,
+ [MO_BEQ] = helper_be_ldlinkq_mmu,
+};
+
+#define LDEX_HELPER(SUFF, OPC) \
+uint32_t HELPER(ldlink_aa32_i##SUFF)(CPUARMState *env, uint32_t addr, \
+ uint32_t index) \
+{ \
+ CPUArchState *state = env; \
+ TCGMemOpIdx op; \
+ \
+ op = make_memop_idx(OPC, index); \
+ \
+ tcg_target_ulong (*func)(CPUArchState *env, target_ulong addr, \
+ TCGMemOpIdx oi, uintptr_t retaddr); \
+ func = qemu_ldex_helpers[OPC]; \
+ \
+ return (uint32_t)func(state, addr, op, GETRA()); \
+}
+
+LDEX_HELPER(8, MO_UB)
+LDEX_HELPER(16, MO_TEUW)
+LDEX_HELPER(32, MO_TEUL)
+
+uint64_t HELPER(ldlink_aa32_i64)(CPUARMState *env, uint32_t addr,
+ uint32_t index)
+{
+ CPUArchState *state = env;
+ TCGMemOpIdx op;
+
+ op = make_memop_idx(MO_TEQ, index);
+
+ uint64_t (*func)(CPUArchState *env, target_ulong addr,
+ TCGMemOpIdx oi, uintptr_t retaddr);
+ func = qemu_ldex_helpers[MO_TEQ];
+
+ return func(state, addr, op, GETRA());
+}
+
+/* StoreConditional helpers. Use the macro below to access them. */
+static void * const qemu_stex_helpers[16] = {
+ [MO_UB] = helper_ret_stcondb_mmu,
+ [MO_LEUW] = helper_le_stcondw_mmu,
+ [MO_LEUL] = helper_le_stcondl_mmu,
+ [MO_LEQ] = helper_le_stcondq_mmu,
+ [MO_BEUW] = helper_be_stcondw_mmu,
+ [MO_BEUL] = helper_be_stcondl_mmu,
+ [MO_BEQ] = helper_be_stcondq_mmu,
+};
+
+#define STEX_HELPER(SUFF, DATA_TYPE, OPC) \
+uint32_t HELPER(stcond_aa32_i##SUFF)(CPUARMState *env, uint32_t addr, \
+ uint32_t val, uint32_t index) \
+{ \
+ CPUArchState *state = env; \
+ TCGMemOpIdx op; \
+ \
+ op = make_memop_idx(OPC, index); \
+ \
+ tcg_target_ulong (*func)(CPUArchState *env, target_ulong addr, \
+ DATA_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr); \
+ func = qemu_stex_helpers[OPC]; \
+ \
+ return (uint32_t)func(state, addr, val, op, GETRA()); \
+}
+
+STEX_HELPER(8, uint8_t, MO_UB)
+STEX_HELPER(16, uint16_t, MO_TEUW)
+STEX_HELPER(32, uint32_t, MO_TEUL)
+
+uint32_t HELPER(stcond_aa32_i64)(CPUARMState *env, uint32_t addr,
+ uint64_t val, uint32_t index)
+{
+ CPUArchState *state = env;
+ TCGMemOpIdx op;
+
+ op = make_memop_idx(MO_TEQ, index);
+
+ tcg_target_ulong (*func)(CPUArchState *env, target_ulong addr,
+ uint64_t val, TCGMemOpIdx oi, uintptr_t retaddr);
+ func = qemu_stex_helpers[MO_TEQ];
+
+ return (uint32_t)func(state, addr, val, op, GETRA());
+}
--
2.5.3
- [Qemu-devel] [RFC v5 0/6] Slow-path for atomic instruction translation, Alvise Rigo, 2015/09/24
- [Qemu-devel] [RFC v5 1/6] exec.c: Add new exclusive bitmap to ram_list, Alvise Rigo, 2015/09/24
- [Qemu-devel] [RFC v5 6/6] target-arm: translate: Use ld/st excl for atomic insns, Alvise Rigo, 2015/09/24
- [Qemu-devel] [RFC v5 2/6] softmmu: Add new TLB_EXCL flag, Alvise Rigo, 2015/09/24
- [Qemu-devel] [RFC v5 3/6] softmmu: Add helpers for a new slowpath, Alvise Rigo, 2015/09/24
- [Qemu-devel] [RFC v5 4/6] target-arm: Create new runtime helpers for excl accesses,
Alvise Rigo <=
- [Qemu-devel] [RFC v5 5/6] configure: Use slow-path for atomic only when the softmmu is enabled, Alvise Rigo, 2015/09/24