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Re: [Qemu-devel] [PATCH v3 6/6] tcg/mips: Support r6 SEL{NE, EQ}Z instea
From: |
James Hogan |
Subject: |
Re: [Qemu-devel] [PATCH v3 6/6] tcg/mips: Support r6 SEL{NE, EQ}Z instead of MOVN/MOVZ |
Date: |
Wed, 7 Oct 2015 11:34:40 +0100 |
User-agent: |
Mutt/1.5.23 (2014-03-12) |
On Wed, Oct 07, 2015 at 08:46:30PM +1100, Richard Henderson wrote:
> On 10/02/2015 10:24 PM, James Hogan wrote:
> > Extend MIPS movcond implementation to support the SELNEZ/SELEQZ
> > instructions introduced in MIPS r6 (where MOVN/MOVZ have been removed).
> >
> > Whereas the "MOVN/MOVZ rd, rs, rt" instructions have the following
> > semantics:
> > rd = [!]rt ? rs : rd
> >
> > The "SELNEZ/SELEQZ rd, rs, rt" instructions are slightly different:
> > rd = [!]rt ? rs : 0
> >
> > First we ensure that if one of the movcond input values is zero that it
> > comes last (we can swap the input arguments if we invert the condition).
> > This is so that it can exactly match one of the SELNEZ/SELEQZ
> > instructions and avoid the need to emit the other one.
> >
> > Otherwise we emit the opposite instruction first into a temporary
> > register, and OR that into the result:
> > SELNEZ/SELEQZ TMP1, v2, c1
> > SELEQZ/SELNEZ ret, v1, c1
> > OR ret, ret, TMP1
> >
> > Which does the following:
> > ret = cond ? v1 : v2
> >
> > Signed-off-by: James Hogan<address@hidden>
> > Cc: Richard Henderson<address@hidden>
> > Cc: Aurelien Jarno<address@hidden>
>
> Reviewed-by: Richard Henderson <address@hidden>
Thanks for the reviewing!
>
>
> > { INDEX_op_brcond_i32, { "rZ", "rZ" } },
> > +#if !use_mips32r6_instructions
> > { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "0" } },
> > +#else
> > + { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },
> > +#endif
>
>
> The only thing I'd change is preferring positive tests to negative ones. So
> swap the order of these lines, and the sense of the #if.
No problem. Shall I do a full resend for that, or can it be fixed up by
whoever applies?
Cheers
James
>
> Leon, do you want to take this as a mips maintainer, or shall I as tcg
> maintainer?
>
>
> r~
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Description: Digital signature
[Qemu-devel] [PATCH v3 3/6] tcg/mips: Add use_mips32r6_instructions definition, James Hogan, 2015/10/08
[Qemu-devel] [PATCH v3 4/6] tcg/mips: Support r6 JR encoding, James Hogan, 2015/10/08
[Qemu-devel] [PATCH v3 2/6] disas/mips: Add R6 jr/jr.hb to disassembler, James Hogan, 2015/10/08
[Qemu-devel] [PATCH v3 5/6] tcg/mips: Support r6 multiply/divide encodings, James Hogan, 2015/10/08