[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 08/12] Correctly re-init EFER state during INIT IPI
From: |
Eduardo Habkost |
Subject: |
[Qemu-devel] [PULL 08/12] Correctly re-init EFER state during INIT IPI |
Date: |
Mon, 5 Oct 2015 13:06:30 -0300 |
From: Bill Paul <address@hidden>
When doing a re-initialization of a CPU core, the default state is to _not_
have 64-bit long mode enabled. This means the LME (long mode enable) and LMA
(long mode active) bits in the EFER model-specific register should be cleared.
However, the EFER state is part of the CPU environment which is
preserved by do_cpu_init(), so if EFER.LME and EFER.LMA were set at the
time an INIT IPI was received, they will remain set after the init completes.
This is contrary to what the Intel architecture manual describes and what
happens on real hardware, and it leaves the CPU in a weird state that the
guest can't clear.
To fix this, the 'efer' member of the CPUX86State structure has been moved
to an area outside the region preserved by do_cpu_init(), so that it can
be properly re-initialized by x86_cpu_reset().
Signed-off-by: Bill Paul <address@hidden>
CC: Paolo Bonzini <address@hidden>
CC: Richard Henderson <address@hidden>
CC: Eduardo Habkost <address@hidden>
Reviewed-by: Paolo Bonzini <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>
---
target-i386/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 92426dc..8926780 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -833,6 +833,7 @@ typedef struct CPUX86State {
BNDReg bnd_regs[4];
BNDCSReg bndcs_regs;
uint64_t msr_bndcfgs;
+ uint64_t efer;
/* Beginning of state preserved by INIT (dummy marker). */
struct {} start_init_save;
@@ -865,7 +866,6 @@ typedef struct CPUX86State {
uint32_t sysenter_cs;
target_ulong sysenter_esp;
target_ulong sysenter_eip;
- uint64_t efer;
uint64_t star;
uint64_t vm_hsave;
--
2.1.0
- [Qemu-devel] [PULL 00/12] X86 queue, 2015-10-05, Eduardo Habkost, 2015/10/08
- [Qemu-devel] [PULL 12/12] icc_bus: drop the unused files, Eduardo Habkost, 2015/10/08
- [Qemu-devel] [PULL 01/12] cpu: Introduce X86CPUTopoInfo structure for argument simplification, Eduardo Habkost, 2015/10/08
- [Qemu-devel] [PULL 03/12] target-i386: Convert kvm_default_*features to property/value pairs, Eduardo Habkost, 2015/10/08
- [Qemu-devel] [PULL 04/12] target-i386: Move breakpoint related functions to new file, Eduardo Habkost, 2015/10/08
- [Qemu-devel] [PULL 07/12] target-i386: add ABM to Haswell* and Broadwell* CPU models, Eduardo Habkost, 2015/10/08
- [Qemu-devel] [PULL 06/12] target-i386: get/put MSR_TSC_AUX across reset and migration, Eduardo Habkost, 2015/10/08
- [Qemu-devel] [PULL 09/12] apic: move APIC's MMIO region mapping into APIC, Eduardo Habkost, 2015/10/08
- Re: [Qemu-devel] [PULL 00/12] X86 queue, 2015-10-05, Peter Maydell, 2015/10/08
- [Qemu-devel] [PULL 08/12] Correctly re-init EFER state during INIT IPI,
Eduardo Habkost <=
- [Qemu-devel] [PULL 02/12] vl: Add another sanity check to smp_parse() function, Eduardo Habkost, 2015/10/08
- [Qemu-devel] [PULL 10/12] x86: use new method to correct reset sequence, Eduardo Habkost, 2015/10/08
- [Qemu-devel] [PULL 05/12] target-i386: Make check_hw_breakpoints static, Eduardo Habkost, 2015/10/08
- [Qemu-devel] [PULL 11/12] cpu/apic: drop icc bus/bridge, Eduardo Habkost, 2015/10/08