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[Qemu-devel] [PULL 04/10] tcg-opc.h: Simplify insn_start def
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 04/10] tcg-opc.h: Simplify insn_start def |
Date: |
Wed, 21 Oct 2015 11:42:53 -1000 |
From: James Hogan <address@hidden>
We already have a TLADDR_ARGS definition, so rearrange the order
slightly and use it in the definition of insn_start, instead of
having an #ifdef.
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: James Hogan <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
---
tcg/tcg-opc.h | 13 +++++--------
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index c6f9570..6d0410c 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -173,18 +173,15 @@ DEF(muls2_i64, 2, 2, 0, IMPL64 |
IMPL(TCG_TARGET_HAS_muls2_i64))
DEF(muluh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i64))
DEF(mulsh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i64))
+#define TLADDR_ARGS (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2)
+#define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2)
+
/* QEMU specific */
-#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
-DEF(insn_start, 0, 0, 2 * TARGET_INSN_START_WORDS, TCG_OPF_NOT_PRESENT)
-#else
-DEF(insn_start, 0, 0, TARGET_INSN_START_WORDS, TCG_OPF_NOT_PRESENT)
-#endif
+DEF(insn_start, 0, 0, TLADDR_ARGS * TARGET_INSN_START_WORDS,
+ TCG_OPF_NOT_PRESENT)
DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END)
DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END)
-#define TLADDR_ARGS (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2)
-#define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2)
-
DEF(qemu_ld_i32, 1, TLADDR_ARGS, 1,
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
DEF(qemu_st_i32, 0, TLADDR_ARGS + 1, 1,
--
2.4.3
- [Qemu-devel] [PULL 00/10] collected tcg patches, Richard Henderson, 2015/10/21
- [Qemu-devel] [PULL 01/10] tcg/ppc: Adjust exit_tb for change in prologue placement, Richard Henderson, 2015/10/21
- [Qemu-devel] [PULL 02/10] tcg/ppc: Revise goto_tb implementation, Richard Henderson, 2015/10/21
- [Qemu-devel] [PULL 03/10] tcg/ppc: Prefer mask over andi., Richard Henderson, 2015/10/21
- [Qemu-devel] [PULL 04/10] tcg-opc.h: Simplify insn_start def,
Richard Henderson <=
- [Qemu-devel] [PULL 05/10] disas/mips: Add R6 jr/jr.hb to disassembler, Richard Henderson, 2015/10/21
- [Qemu-devel] [PULL 06/10] tcg/mips: Add use_mips32r6_instructions definition, Richard Henderson, 2015/10/21
- [Qemu-devel] [PULL 07/10] tcg/mips: Support r6 JR encoding, Richard Henderson, 2015/10/21
- [Qemu-devel] [PULL 09/10] tcg/mips: Support r6 SEL{NE, EQ}Z instead of MOVN/MOVZ, Richard Henderson, 2015/10/21
- [Qemu-devel] [PULL 08/10] tcg/mips: Support r6 multiply/divide encodings, Richard Henderson, 2015/10/21
- [Qemu-devel] [PULL 10/10] cpu-exec: Add "nochain" debug flag, Richard Henderson, 2015/10/21
- Re: [Qemu-devel] [PULL 00/10] collected tcg patches, Peter Maydell, 2015/10/22