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[Qemu-devel] [PATCH v5 12/14] target-arm: Add S2 translation to 32bit S1
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v5 12/14] target-arm: Add S2 translation to 32bit S1 PTWs |
Date: |
Mon, 26 Oct 2015 14:02:05 +0100 |
From: "Edgar E. Iglesias" <address@hidden>
Add support for applying S2 translation to 32bit S1
page-table walks.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target-arm/helper.c | 22 +++++++++++++++++-----
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 76dfd33..3857c0b 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -6230,11 +6230,19 @@ static hwaddr S1_ptw_translate(CPUARMState *env,
ARMMMUIdx mmu_idx,
* was being done for a CPU load/store or an address translation instruction
* (but not if it was for a debug access).
*/
-static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure)
+static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
+ ARMMMUIdx mmu_idx, uint32_t *fsr,
+ ARMMMUFaultInfo *fi)
{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
MemTxAttrs attrs = {};
attrs.secure = is_secure;
+ addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
+ if (fi->s1ptw) {
+ return 0;
+ }
return address_space_ldl(cs->as, addr, attrs, NULL);
}
@@ -6278,7 +6286,8 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t
address,
code = 5;
goto do_fault;
}
- desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
+ desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
+ mmu_idx, fsr, fi);
type = (desc & 3);
domain = (desc >> 5) & 0x0f;
if (regime_el(env, mmu_idx) == 1) {
@@ -6314,7 +6323,8 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t
address,
/* Fine pagetable. */
table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
}
- desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
+ desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
+ mmu_idx, fsr, fi);
switch (desc & 3) {
case 0: /* Page translation fault. */
code = 7;
@@ -6395,7 +6405,8 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t
address,
code = 5;
goto do_fault;
}
- desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
+ desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
+ mmu_idx, fsr, fi);
type = (desc & 3);
if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
/* Section translation fault, or attempt to use the encoding
@@ -6446,7 +6457,8 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t
address,
ns = extract32(desc, 3, 1);
/* Lookup l2 entry. */
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
- desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx));
+ desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
+ mmu_idx, fsr, fi);
ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
switch (desc & 3) {
case 0: /* Page translation fault. */
--
1.9.1
- [Qemu-devel] [PATCH v5 03/14] target-arm: lpae: Move declaration of t0sz and t1sz, (continued)
- [Qemu-devel] [PATCH v5 03/14] target-arm: lpae: Move declaration of t0sz and t1sz, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 05/14] target-arm: lpae: Replace tsz with computed inputsize, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 04/14] target-arm: Add support for AArch32 S2 negative t0sz, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 06/14] target-arm: lpae: Rename granule_sz to stride, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 07/14] target-arm: Add computation of starting level for S2 PTW, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 08/14] target-arm: Add support for S2 page-table protection bits, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 09/14] target-arm: Avoid inline for get_phys_addr, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 10/14] target-arm: Add ARMMMUFaultInfo, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 11/14] target-arm: Add S2 translation to 64bit S1 PTWs, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 13/14] target-arm: Route S2 MMU faults to EL2, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 12/14] target-arm: Add S2 translation to 32bit S1 PTWs,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v5 14/14] target-arm: Add support for S1 + S2 MMU translations, Edgar E. Iglesias, 2015/10/26
- Re: [Qemu-devel] [PATCH v5 00/14] arm: Steps towards EL2 support round 5, Peter Maydell, 2015/10/27