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From: | Jean-Christophe DUBOIS |
Subject: | Re: [Qemu-devel] [PATCH] i.MX: add support for lower and upper interrupt in GPIO. |
Date: | Wed, 28 Oct 2015 08:10:18 +0100 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 |
Le 27/10/2015 23:41, Peter Crosthwaite
a écrit :
Well, I am not part of Freescale so I just don't know anything about internal implementation details of this IP and its use inside the SOC. What we can say is that the dual interrupt version (i.MX6) is newer than the single one (i.MX31, i.MX25). So my guess is that this is an evolution of the IP and the goal was to make GPIO interrupt handling easier, faster and prioritisable.
At the SOC level I was planning to set (or not) the new property and to assign 1 (or 2) IRQ to the device. Regards JC
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