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[Qemu-devel] [PULL 8/9] target-mips: add SIGRIE instruction
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 8/9] target-mips: add SIGRIE instruction |
Date: |
Fri, 30 Oct 2015 15:00:51 +0000 |
From: Yongbok Kim <address@hidden>
Add SIGRIE (Signal Reserved Instruction Exception) for both MIPS and
microMIPS.
The instruction allows to use the 16-bit code field for software use.
This instruction is introduced by and required as of Release 6.
Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/translate.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index bacac2b..5626647 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -323,6 +323,7 @@ enum {
OPC_TLTIU = (0x0B << 16) | OPC_REGIMM,
OPC_TEQI = (0x0C << 16) | OPC_REGIMM,
OPC_TNEI = (0x0E << 16) | OPC_REGIMM,
+ OPC_SIGRIE = (0x17 << 16) | OPC_REGIMM,
OPC_SYNCI = (0x1F << 16) | OPC_REGIMM,
OPC_DAHI = (0x06 << 16) | OPC_REGIMM,
@@ -12031,7 +12032,8 @@ enum {
LSA = 0x0f,
ALIGN = 0x1f,
EXT = 0x2c,
- POOL32AXF = 0x3c
+ POOL32AXF = 0x3c,
+ SIGRIE = 0x3f
};
/* POOL32AXF encoding of minor opcode field extension */
@@ -13655,6 +13657,10 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
case BREAK32:
generate_exception_end(ctx, EXCP_BREAK);
break;
+ case SIGRIE:
+ check_insn(ctx, ISA_MIPS32R6);
+ generate_exception_end(ctx, EXCP_RI);
+ break;
default:
pool32a_invalid:
MIPS_INVAL("pool32a");
@@ -18973,6 +18979,10 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_trap(ctx, op1, rs, -1, imm);
break;
+ case OPC_SIGRIE:
+ check_insn(ctx, ISA_MIPS32R6);
+ generate_exception_end(ctx, EXCP_RI);
+ break;
case OPC_SYNCI:
check_insn(ctx, ISA_MIPS32R2);
/* Break the TB to be able to sync copied instructions
--
2.1.0
- [Qemu-devel] [PULL 0/9] target-mips queue, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 1/9] target-mips: move the test for enabled interrupts to a separate function, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 5/9] hw/mips_malta: Fix KVM PC initialisation, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 9/9] target-mips: fix updating XContext on mmu exception, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 2/9] target-mips: implement the CPU wake-up on non-enabled interrupts in R6, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 6/9] target-mips: add PC, XNP reg numbers to RDHWR, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 3/9] target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 4/9] target-mips: Add enum for BREAK32, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 7/9] target-mips: Set Config5.XNP for R6 cores, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 8/9] target-mips: add SIGRIE instruction,
Leon Alrae <=
- Re: [Qemu-devel] [PULL 0/9] target-mips queue, Peter Maydell, 2015/10/30