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Re: [Qemu-devel] [Qemu-ppc] [PATCH 16/77] ppc: Get out of emulation on S
From: |
David Gibson |
Subject: |
Re: [Qemu-devel] [Qemu-ppc] [PATCH 16/77] ppc: Get out of emulation on SMT "OR" ops |
Date: |
Mon, 16 Nov 2015 16:40:18 +1100 |
User-agent: |
Mutt/1.5.23 (2015-06-09) |
On Wed, Nov 11, 2015 at 11:27:29AM +1100, Benjamin Herrenschmidt wrote:
> Otherwise tight loops at smt_low for example, which OPAL does,
> eat so much CPU that we can't boot a kernel anymore. With that,
> I can boot 8 CPUs just fine with powernv.
>
> Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
> ---
> target-ppc/translate.c | 19 +++++++++++++++++--
> 1 file changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 3974cd2..e8bbd59 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -1396,6 +1396,19 @@ GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
> /* nor & nor. */
> GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
>
> +#if defined(TARGET_PPC64)
> +static void gen_pause(DisasContext *ctx)
> +{
> + TCGv_i32 t0 = tcg_const_i32(0);
> + tcg_gen_st_i32(t0, cpu_env,
> + -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
> + tcg_temp_free_i32(t0);
> +
> + /* Stop translation, this gives other CPUs a chance to run */
> + gen_exception_err(ctx, EXCP_HLT, 1);
> +}
> +#endif /* defined(TARGET_PPC64) */
> +
> /* or & or. */
> static void gen_or(DisasContext *ctx)
> {
> @@ -1468,6 +1481,10 @@ static void gen_or(DisasContext *ctx)
> tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
> gen_store_spr(SPR_PPR, t0);
> tcg_temp_free(t0);
> + /* Pause us out of TCG otherwise spin loops with smt_low
> + * eat too much CPU and the kernel hangs
> + */
> + gen_pause(ctx);
> }
> #endif
> }
> @@ -1493,8 +1510,6 @@ static void gen_ori(DisasContext *ctx)
> target_ulong uimm = UIMM(ctx->opcode);
>
> if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
> - /* NOP */
> - /* XXX: should handle special NOPs for POWER series */
> return;
> }
> tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- Re: [Qemu-devel] [Qemu-ppc] [PATCH 00/77] ppc: Add "native" POWER8 platform, (continued)
Re: [Qemu-devel] [Qemu-ppc] [PATCH 00/77] ppc: Add "native" POWER8 platform, Stewart Smith, 2015/11/10
[Qemu-devel] [PATCH 24/77] ppc: Move exception generation code out of line, Benjamin Herrenschmidt, 2015/11/10
[Qemu-devel] [PATCH 37/77] ppc/xics: Split ICS into base class and "simple" implementation, Benjamin Herrenschmidt, 2015/11/10
[Qemu-devel] [PATCH 10/77] ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV, Benjamin Herrenschmidt, 2015/11/10
[Qemu-devel] [PATCH 22/77] ppc: Add real mode CI load/store instructions for P7 and P8, Benjamin Herrenschmidt, 2015/11/10
[Qemu-devel] [PATCH 15/77] ppc: Fix sign extension issue in mtmsr(d) emulation, Benjamin Herrenschmidt, 2015/11/10
[Qemu-devel] [PATCH 16/77] ppc: Get out of emulation on SMT "OR" ops, Benjamin Herrenschmidt, 2015/11/10
- Re: [Qemu-devel] [Qemu-ppc] [PATCH 16/77] ppc: Get out of emulation on SMT "OR" ops,
David Gibson <=
[Qemu-devel] [PATCH 48/77] ppc/pnv: Add model for Power8 PHB3 PCIe Host bridge, Benjamin Herrenschmidt, 2015/11/10