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[Qemu-devel] [PATCH] hw/arm_gic: Correctly restore nested irq priority


From: Francois Baldassari
Subject: [Qemu-devel] [PATCH] hw/arm_gic: Correctly restore nested irq priority
Date: Tue, 17 Nov 2015 01:12:37 -0800

Upon activating an interrupt, set the corresponding priority bit in the APR/NSAPR registers without touching the currently set bits. In the event of nested interrupts, the GIC will then have the information it needs to restore the priority of the pre-empted interrupt once the higher priority interrupt finishes execution.

Signed-off-by: François Baldassari <address@hidden>
---
First time submitter here - I tried to follow http://qemu-project.org/Contribute/SubmitAPatch as best I could but do let me know if I missed anything.

 hw/intc/arm_gic.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index d71aeb8..13e297d 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -254,9 +254,9 @@ static void gic_activate_irq(GICState *s, int cpu, int irq)
     int bitno = preemption_level % 32;
 
     if (gic_has_groups(s) && GIC_TEST_GROUP(irq, (1 << cpu))) {
-        s->nsapr[regno][cpu] &= (1 << bitno);
+        s->nsapr[regno][cpu] |= (1 << bitno);
     } else {
-        s->apr[regno][cpu] &= (1 << bitno);
+        s->apr[regno][cpu] |= (1 << bitno);
     }
 
     s->running_priority[cpu] = prio;
--
2.4.0



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