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[Qemu-devel] [PATCH v5 2/7] mips/kvm: Implement PRid CP0 register
From: |
James Hogan |
Subject: |
[Qemu-devel] [PATCH v5 2/7] mips/kvm: Implement PRid CP0 register |
Date: |
Wed, 3 Feb 2016 17:16:48 +0000 |
Implement saving and restoring to KVM state of the Processor ID (PRid)
CP0 register. This allows QEMU to control the PRid exposed to the guest
instead of using the default set by KVM.
Signed-off-by: James Hogan <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: Aurelien Jarno <address@hidden>
---
target-mips/kvm.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/target-mips/kvm.c b/target-mips/kvm.c
index 8bd74385110b..c5bf44da9f02 100644
--- a/target-mips/kvm.c
+++ b/target-mips/kvm.c
@@ -228,6 +228,7 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int
level)
#define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
#define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
#define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
+#define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0)
#define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id,
@@ -520,6 +521,11 @@ static int kvm_mips_put_cp0_registers(CPUState *cs, int
level)
DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__, err);
ret = err;
}
+ err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid);
+ if (err < 0) {
+ DPRINTF("%s: Failed to put CP0_PRID (%d)\n", __func__, err);
+ ret = err;
+ }
err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
&env->CP0_ErrorEPC);
if (err < 0) {
@@ -606,6 +612,11 @@ static int kvm_mips_get_cp0_registers(CPUState *cs)
DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__, err);
ret = err;
}
+ err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid);
+ if (err < 0) {
+ DPRINTF("%s: Failed to get CP0_PRID (%d)\n", __func__, err);
+ ret = err;
+ }
err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
&env->CP0_ErrorEPC);
if (err < 0) {
--
2.4.10
- [Qemu-devel] [PATCH v5 0/7] mips/kvm: Support FPU & SIMD (MSA) in MIPS KVM guests, James Hogan, 2016/02/03
- [Qemu-devel] [PATCH v5 4/7] mips/kvm: Support unsigned KVM registers, James Hogan, 2016/02/03
- [Qemu-devel] [PATCH v5 5/7] mips/kvm: Support signed 64-bit KVM registers, James Hogan, 2016/02/03
- [Qemu-devel] [PATCH v5 1/7] mips/kvm: Remove a couple of noisy DPRINTFs, James Hogan, 2016/02/03
- [Qemu-devel] [PATCH v5 2/7] mips/kvm: Implement PRid CP0 register,
James Hogan <=
- [Qemu-devel] [PATCH v5 3/7] mips/kvm: Implement Config CP0 registers, James Hogan, 2016/02/03
- [Qemu-devel] [PATCH v5 6/7] mips/kvm: Support FPU in MIPS KVM guests, James Hogan, 2016/02/03
- [Qemu-devel] [PATCH v5 7/7] mips/kvm: Support MSA in MIPS KVM guests, James Hogan, 2016/02/03
- Re: [Qemu-devel] [PATCH v5 0/7] mips/kvm: Support FPU & SIMD (MSA) in MIPS KVM guests, Leon Alrae, 2016/02/04