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Re: [Qemu-devel] [PATCH v2 5/5] target-arm: Unmask PMU bits in debug fea
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v2 5/5] target-arm: Unmask PMU bits in debug feature register |
Date: |
Tue, 9 Feb 2016 17:43:26 +0000 |
On 6 February 2016 at 00:55, Alistair Francis
<address@hidden> wrote:
> The previously missing registers are now present in QEMU.
I think we're still missing some:
32 bit version present, 64 bit version missing:
PMSWINC
PMINTENSET
not implemented in 32 bit either:
PMOVSCLR (I think this is only in PMUv3 so needs care as to
which CPUs we define it on)
> Signed-off-by: Christopher Covington <address@hidden>
> Signed-off-by: Alistair Francis <address@hidden>
> ---
>
> target-arm/helper.c | 7 +------
> 1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index b4bf6fa..1775768 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -4267,12 +4267,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
> .access = PL1_R, .type = ARM_CP_CONST,
> - /* We mask out the PMUVer field, because we don't currently
> - * implement the PMU. Not advertising it prevents the guest
> - * from trying to use it and getting UNDEFs on registers we
> - * don't implement.
> - */
> - .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
> + .resetvalue = cpu->id_aa64dfr0 },
> { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
> .access = PL1_R, .type = ARM_CP_CONST,
> --
> 2.5.0
>
thanks
-- PMM
- Re: [Qemu-devel] [PATCH v2 1/5] target-arm: Add the pmceid0 and pmceid1 registers, (continued)
[Qemu-devel] [PATCH v2 2/5] target-arm: Add Some of the performance monitor registers, Alistair Francis, 2016/02/05
[Qemu-devel] [PATCH v2 3/5] target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers, Alistair Francis, 2016/02/05
[Qemu-devel] [PATCH v2 4/5] target-arm: Add PMUSERENR_EL0 register, Alistair Francis, 2016/02/05
[Qemu-devel] [PATCH v2 5/5] target-arm: Unmask PMU bits in debug feature register, Alistair Francis, 2016/02/05
- Re: [Qemu-devel] [PATCH v2 5/5] target-arm: Unmask PMU bits in debug feature register,
Peter Maydell <=