[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 12/15] target-arm: Implement checking of fired watchp
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 12/15] target-arm: Implement checking of fired watchpoint |
Date: |
Tue, 9 Feb 2016 18:43:02 +0000 |
From: Sergey Fedorov <address@hidden>
ARM stops before access to a location covered by watchpoint. Also, QEMU
watchpoint fire is not necessarily an architectural watchpoint match.
Unfortunately, that is hardly possible to ignore a fired watchpoint in
debug exception handler. So move watchpoint check from debug exception
handler to the dedicated watchpoint checking callback.
Signed-off-by: Sergey Fedorov <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.c | 1 +
target-arm/internals.h | 3 +++
target-arm/op_helper.c | 35 +++++++++++++++++++++--------------
3 files changed, 25 insertions(+), 14 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 7ddbf3d..f2393cd 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -1483,6 +1483,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void
*data)
cc->gdb_arch_name = arm_gdb_arch_name;
cc->gdb_stop_before_watchpoint = true;
cc->debug_excp_handler = arm_debug_excp_handler;
+ cc->debug_check_watchpoint = arm_debug_check_watchpoint;
cc->disas_set_info = arm_disas_set_info;
diff --git a/target-arm/internals.h b/target-arm/internals.h
index a648c1e..70bec4a 100644
--- a/target-arm/internals.h
+++ b/target-arm/internals.h
@@ -409,6 +409,9 @@ void hw_breakpoint_update(ARMCPU *cpu, int n);
*/
void hw_breakpoint_update_all(ARMCPU *cpu);
+/* Callback function for checking if a watchpoint should trigger. */
+bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
+
/* Callback function for when a watchpoint or breakpoint triggers. */
void arm_debug_excp_handler(CPUState *cs);
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 313c0f8..bd48549 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -976,6 +976,16 @@ void HELPER(check_breakpoints)(CPUARMState *env)
}
}
+bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
+{
+ /* Called by core code when a CPU watchpoint fires; need to check if this
+ * is also an architectural watchpoint match.
+ */
+ ARMCPU *cpu = ARM_CPU(cs);
+
+ return check_watchpoints(cpu);
+}
+
void arm_debug_excp_handler(CPUState *cs)
{
/* Called by core code when a watchpoint or breakpoint fires;
@@ -987,23 +997,20 @@ void arm_debug_excp_handler(CPUState *cs)
if (wp_hit) {
if (wp_hit->flags & BP_CPU) {
+ bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0;
+ bool same_el = arm_debug_target_el(env) == arm_current_el(env);
+
cs->watchpoint_hit = NULL;
- if (check_watchpoints(cpu)) {
- bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0;
- bool same_el = arm_debug_target_el(env) == arm_current_el(env);
-
- if (extended_addresses_enabled(env)) {
- env->exception.fsr = (1 << 9) | 0x22;
- } else {
- env->exception.fsr = 0x2;
- }
- env->exception.vaddress = wp_hit->hitaddr;
- raise_exception(env, EXCP_DATA_ABORT,
- syn_watchpoint(same_el, 0, wnr),
- arm_debug_target_el(env));
+
+ if (extended_addresses_enabled(env)) {
+ env->exception.fsr = (1 << 9) | 0x22;
} else {
- cpu_resume_from_signal(cs, NULL);
+ env->exception.fsr = 0x2;
}
+ env->exception.vaddress = wp_hit->hitaddr;
+ raise_exception(env, EXCP_DATA_ABORT,
+ syn_watchpoint(same_el, 0, wnr),
+ arm_debug_target_el(env));
}
} else {
uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
--
1.9.1
- [Qemu-devel] [PULL 00/15] target-arm queue, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 13/15] sd: limit 'req.cmd' while using as an array index, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 14/15] hw/arm/virt: fix max-cpus check, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 15/15] bcm2835_property: implement "get board revision" query, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 09/15] target-arm: Fix IL bit reported for Thumb coprocessor traps, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 10/15] target-arm: Fix IL bit reported for Thumb VFP and Neon traps, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 03/15] target-arm: Use access_trap_aa32s_el1() for SCR and MVBAR, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 07/15] target-arm: Enable EL3 for Cortex-A53 and Cortex-A57, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 12/15] target-arm: Implement checking of fired watchpoint,
Peter Maydell <=
- [Qemu-devel] [PULL 11/15] cpu: Add callback to check architectural watchpoint match, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 08/15] target-arm: Correct misleading 'is_thumb' syn_* parameter names, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 02/15] target-arm: Implement MDCR_EL3 and SDCR, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 01/15] target-arm: Fix typo in comment in arm_is_secure_below_el3(), Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 04/15] target-arm: Update arm_generate_debug_exceptions() to handle EL2/EL3, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 06/15] target-arm: Implement NSACR trapping behaviour, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 05/15] target-arm: Add isread parameter to CPAccessFns, Peter Maydell, 2016/02/09
- Re: [Qemu-devel] [PULL 00/15] target-arm queue, Peter Maydell, 2016/02/11