Re: [Qemu-devel] [RFC 0/1] riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G)

[Peter Maydell]

On 19 February 2016 at 01:02, Sagar Karandikar <address@hidden> wrote:
> The patch in this RFC adds support for the RISC-V ISA [1] as a target. It has
> been tested booting Linux and FreeBSD, passes the RISC-V assembly test suite,
> and has had the riscv-torture tester running on it for a couple of weeks now
> without any issues arising.
>
> With this RFC, I mainly wanted to get input on the overall design of the 
> target
> implementation, as well as see if any regular contributors would be interested
> in co-mentoring RISC-V related projects for QEMU's Google Summer of Code with
> me.

This absolutely must be split up into multiple patches -- it is currently
a single patch which adds 13000 lines of code. This is absolutely not
reviewable. You should be looking at something around 100 lines of
code a patch, or less.

> Some notes/questions:
> - This provides support only for the 64-bit version of the ISA and full system
>   emulation (no user-mode)
> - This currently applies to the 2.5.0 release version. I will bump the
>   underlying codebase, split this into multiple patches, apply style checks
>   before submitting real patches

Yes, please do. I doubt anybody will care to give you much design input
otherwise...

> - The code in target-riscv/fpu-custom-riscv is an updated/modified version of
>   softfloat. Is it okay to submodule this until the FPU behavior in RISC-V
>   is stabilized? (and then later, presumably merge it with the version of
>   softfloat included in QEMU). For current review purposes, I believe 
> everything
>   in this directory can be ignored.

Please use our actual softfloat implementation. If it needs improvements
or bugfixes, then go ahead and make them. We don't want two copies which
differ subtly.

thanks
-- PMM