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[Qemu-devel] [PULL 09/20] target-arm: In v8, make illegal AArch32 mode c
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 09/20] target-arm: In v8, make illegal AArch32 mode changes set PSTATE.IL |
Date: |
Fri, 26 Feb 2016 15:20:14 +0000 |
In v8, the illegal mode changes which are UNPREDICTABLE in v7 are
given architected behaviour:
* the mode field is unchanged
* PSTATE.IL is set (so any subsequent instructions will UNDEF)
* any other CPSR fields are written to as normal
This is pretty much the same behaviour we picked for our
UNPREDICTABLE handling, with the exception that for v8 we
need to set the IL bit.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden
---
target-arm/helper.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 5926b15..ff5f895 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5325,11 +5325,20 @@ void cpsr_write(CPUARMState *env, uint32_t val,
uint32_t mask,
(env->uncached_cpsr & CPSR_M) != CPSR_USER &&
((env->uncached_cpsr ^ val) & mask & CPSR_M)) {
if (bad_mode_switch(env, val & CPSR_M)) {
- /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
- * We choose to ignore the attempt and leave the CPSR M field
- * untouched.
+ /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
+ * v7, and has defined behaviour in v8:
+ * + leave CPSR.M untouched
+ * + allow changes to the other CPSR fields
+ * + set PSTATE.IL
+ * For user changes via the GDB stub, we don't set PSTATE.IL,
+ * as this would be unnecessarily harsh for a user error.
*/
mask &= ~CPSR_M;
+ if (write_type != CPSRWriteByGDBStub &&
+ arm_feature(env, ARM_FEATURE_V8)) {
+ mask |= CPSR_IL;
+ val |= CPSR_IL;
+ }
} else {
switch_mode(env, val & CPSR_M);
}
--
1.9.1
- [Qemu-devel] [PULL 02/20] target-arm: Add write_type argument to cpsr_write(), (continued)
- [Qemu-devel] [PULL 02/20] target-arm: Add write_type argument to cpsr_write(), Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 17/20] sdhci: Revert "add optional quirk property to disable card insertion/removal interrupts", Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 12/20] target-arm: Fix handling of SDCR for 32-bit code, Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 04/20] linux-user: Use restrictive mask when calling cpsr_write(), Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 11/20] target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1, Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 20/20] target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF, Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 13/20] target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps, Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 14/20] ARM: PL061: Checking register r/w accesses to reserved area, Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 07/20] target-arm: Add Hyp mode checks to bad_mode_switch(), Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 15/20] raspi: fix SD card with recent sdhci changes, Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 09/20] target-arm: In v8, make illegal AArch32 mode changes set PSTATE.IL,
Peter Maydell <=
- [Qemu-devel] [PULL 16/20] MAINTAINERS: Add some missing ARM related header files, Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 19/20] target-arm: Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAW, Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 18/20] sdhci: add quirk property for card insert interrupt status on Raspberry Pi, Peter Maydell, 2016/02/26
- Re: [Qemu-devel] [PULL 00/20] target-arm queue, Peter Maydell, 2016/02/26