Re: [Qemu-devel] [PATCH v2 4/8] target-arm: Add more fields to the data abort syndrome generator

[Sergey Fedorov]

On 25.02.2016 20:41, Peter Maydell wrote:
> On 19 February 2016 at 20:04, Edgar E. Iglesias
> <address@hidden> wrote:
> > From: "Edgar E. Iglesias" <address@hidden>
> >
> > Add the following flags to the data abort syndrome generator:
> > * isv - Instruction syndrome valid
> > * sas - Syndrome access size
> > * sse - Syndrome sign extend
> > * srt - Syndrome register transfer
> > * sf  - Sixty-Four bit register width
> > * ar  - Acquire/Release
> >
> > These flags are not yet used, so this patch has no functional change.
> >
> > Signed-off-by: Edgar E. Iglesias <address@hidden>
> > ---
> >   target-arm/internals.h | 20 ++++++++++++++++++--
> >   target-arm/op_helper.c |  8 ++++++--
> >   2 files changed, 24 insertions(+), 4 deletions(-)
> >
> > diff --git a/target-arm/internals.h b/target-arm/internals.h
> > index 34e2688..4e9d9f5 100644
> > --- a/target-arm/internals.h
> > +++ b/target-arm/internals.h
> > @@ -383,13 +383,29 @@ static inline uint32_t syn_insn_abort(int same_el, int 
> > ea, int s1ptw, int fsc)
> >           | (ea << 9) | (s1ptw << 7) | fsc;
> >   }
> >
> > -static inline uint32_t syn_data_abort(int same_el, int ea, int cm, int s1ptw,
> > +static inline uint32_t syn_data_abort(int same_el, int isv,
> > +                                      int sas, int sse, int srt,
> > +                                      int sf, int ar,
> > +                                      int ea, int cm, int s1ptw,
> >                                         int wnr, int fsc,
> >                                         bool is_16bit)
> Everywhere we call this (both now and once the full patchset has
> been applied) isv is a constant (either 0 or 1). I think it might
> be cleaner to define both a syn_data_abort_with_isv() and a
> syn_data_abort_no_isv(). Then the no_isv version doesn't need all
> the arguments that are zeroes.

Alternatively, we could define a function similar to 
LSInstructionSyndrome from ARMv8 ARM pseudocode, but which will pack the 
instruction syndrome from its components into a value of ISS<24:14>.

Best regards,
Sergey