Re: [Qemu-devel] [PATCH 2/3] i.MX: Add the Freescale SPI Controller

[Peter Crosthwaite]

On Tue, Feb 16, 2016 at 9:15 AM, mar.krzeminski
<address@hidden> wrote:
>
>
> W dniu 15.02.2016 o 23:43, Jean-Christophe DUBOIS pisze:
>
>> Le 15/02/2016 17:46, mar.krzeminski a écrit :
>>>
>>>
>>>
>>> W dniu 15.02.2016 o 11:18, Jean-Christophe DUBOIS pisze:
>>>>
>>>> Le 14/02/2016 20:17, mar.krzeminski a écrit :
>>>>>
>>>>>

>>>>>> controller is working. Now this information (the number of bits actually
>>>>>> transferred) does not seem to be conveyed by the QEMU SSI API. So it is 
>>>>>> my
>>>>>> understanding that it is up to the EEPROM to only consider the bits it is
>>>>>> designed to work with.
>>>>>
>>>>> Current SSI API does not have these information, even more, the flash
>>>>> model assumes that data width will be one byte - see m25p80_transfer8 in
>>>>> m25p80.c. There you can also find sst25vf016b model,
>>>>> and with you current implementation it will not work. In my comment I
>>>>> mean only current ssi usage not the real world.
>>>>
>>>>
>>>> OK, so to summarize, at present time all QEMU SPI slave devices are
>>>> expecting to receive (and provide) data at a byte level only (even if the
>>>> QEMU SSI API is capable of 4 bytes access). So I need to split the (up to) 
>>>> 4
>>>> bytes access of the i.MX SPI master in 1 to 4 single byte access (depending
>>>> on the burst size).
>>>>
>>> Yes.
>>> I think about your idea to add interface to set transfer length fo SSI
>>> API. The question is, if someone really need such feature.
>>

I think so.

>>
>> Well, obviously, memory (or even LCD screen) are not good candidate for
>> access that are not byte aligned. I guess other type of devices (like an ADC
>> or a DAC) might work on 10, 12 (or other size) bits and accept more uncommon
>> access pattern. After all the i.MX SPI controller could handle any SPI burst
>> length between 1 and 4096 bits.
>>
>> Now I guess that such devices DAC/ADC are more difficult to emulate in a
>> useful way inside QEMU. So this might not be very popular and therefore not
>> very useful. It might not be worth the trouble inside QEMU ...
>>
> Modern flash memories have dummy clock cycles for fast operation commands,
> so instead of sending 12 bits I need to call 12 times ssi_trasfer.
> Having such feature could also allow to emulate QSPI and family transfer
> modes, but I guess all of this it is corner case...
>

This keeps coming up so the demand is less corner case than we think.

Regards,
Peter

> Thanks,
> Marcin
>>>