[Qemu-devel] [PULL v2 00/21] target-mips queue for 2.6

[Leon Alrae]

Here's version 2 with qapi/error.h includes.

Thanks,
Leon

Cc: Peter Maydell <address@hidden>
Cc: Aurelien Jarno <address@hidden>

The following changes since commit 553934db664ecee676650fac0330dceff3531736:

  Merge remote-tracking branch 'remotes/cody/tags/block-pull-request' into 
staging (2016-03-29 19:54:49 +0100)

are available in the git repository at:

  git://github.com/lalrae/qemu.git tags/mips-20160329-2

for you to fetch changes up to f6d4dd810983fdf3d1c9fb81838167efef63d1c8:

  target-mips: add MAAR, MAARI register (2016-03-30 09:14:00 +0100)

----------------------------------------------------------------
MIPS patches 2016-03-29

Changes:
* add initial MIPS CPS support
* implement ITU block
* implement MAAR

----------------------------------------------------------------
Leon Alrae (17):
      hw/mips: implement generic MIPS Coherent Processing System container
      hw/mips/cps: create GCR block inside CPS
      hw/mips: add initial Cluster Power Controller support
      hw/mips/cps: create CPC block inside CPS
      hw/mips_malta: remove CPUMIPSState from the write_bootloader()
      hw/mips_malta: remove redundant irq and clock init
      hw/mips_malta: move CPU creation to a separate function
      hw/mips_malta: add CPS to Malta board
      target-mips: enable CM GCR in MIPS64R6-generic CPU
      hw/mips: implement ITC Configuration Tags and Storage Cells
      hw/mips: implement ITC Storage - Control View
      hw/mips: implement ITC Storage - Empty/Full Sync and Try Views
      hw/mips: implement ITC Storage - P/V Sync and Try Views
      hw/mips: implement ITC Storage - Bypass View
      target-mips: check CP0 enabled for CACHE instruction also in R6
      target-mips: make ITC Configuration Tags accessible to the CPU
      hw/mips/cps: enable ITU for multithreading processors

Yongbok Kim (4):
      target-mips: add CMGCRBase register
      hw/mips: add initial Global Config Register support
      target-mips: use CP0_CHECK for gen_m{f|t}hc0
      target-mips: add MAAR, MAARI register

 default-configs/mips-softmmu-common.mak |   2 +
 hw/mips/Makefile.objs                   |   1 +
 hw/mips/cps.c                           | 180 +++++++++++
 hw/mips/mips_malta.c                    | 118 ++++---
 hw/misc/Makefile.objs                   |   3 +
 hw/misc/mips_cmgcr.c                    | 160 ++++++++++
 hw/misc/mips_cpc.c                      | 177 +++++++++++
 hw/misc/mips_itu.c                      | 526 ++++++++++++++++++++++++++++++++
 include/hw/mips/cps.h                   |  46 +++
 include/hw/misc/mips_cmgcr.h            |  59 ++++
 include/hw/misc/mips_cpc.h              |  47 +++
 include/hw/misc/mips_itu.h              |  72 +++++
 target-mips/cpu.h                       |  16 +-
 target-mips/helper.h                    |   9 +
 target-mips/machine.c                   |   6 +-
 target-mips/op_helper.c                 |  85 +++++-
 target-mips/translate.c                 | 189 +++++++++---
 target-mips/translate_init.c            |   6 +-
 18 files changed, 1623 insertions(+), 79 deletions(-)
 create mode 100644 hw/mips/cps.c
 create mode 100644 hw/misc/mips_cmgcr.c
 create mode 100644 hw/misc/mips_cpc.c
 create mode 100644 hw/misc/mips_itu.c
 create mode 100644 include/hw/mips/cps.h
 create mode 100644 include/hw/misc/mips_cmgcr.h
 create mode 100644 include/hw/misc/mips_cpc.h
 create mode 100644 include/hw/misc/mips_itu.h