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[Qemu-devel] [PULL v2 07/21] hw/mips_malta: remove CPUMIPSState from the
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL v2 07/21] hw/mips_malta: remove CPUMIPSState from the write_bootloader() |
Date: |
Wed, 30 Mar 2016 09:49:48 +0100 |
Remove CPUMIPSState from the write_bootloader() argument list as it
is not used in the function.
Signed-off-by: Leon Alrae <address@hidden>
---
hw/mips/mips_malta.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 4ff1bb2..609f6dc 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -608,8 +608,8 @@ static void network_init(PCIBus *pci_bus)
a3 - RAM size in bytes
*/
-static void write_bootloader (CPUMIPSState *env, uint8_t *base,
- int64_t run_addr, int64_t kernel_entry)
+static void write_bootloader(uint8_t *base, int64_t run_addr,
+ int64_t kernel_entry)
{
uint32_t *p;
@@ -1063,11 +1063,11 @@ void mips_malta_init(MachineState *machine)
loaderparams.initrd_filename = initrd_filename;
kernel_entry = load_kernel();
- write_bootloader(env, memory_region_get_ram_ptr(bios),
+ write_bootloader(memory_region_get_ram_ptr(bios),
bootloader_run_addr, kernel_entry);
if (kvm_enabled()) {
/* Write the bootloader code @ the end of RAM, 1MB reserved */
- write_bootloader(env, memory_region_get_ram_ptr(ram_low_preio) +
+ write_bootloader(memory_region_get_ram_ptr(ram_low_preio) +
ram_low_size,
bootloader_run_addr, kernel_entry);
}
--
2.1.0
- [Qemu-devel] [PULL v2 03/21] hw/mips: add initial Global Config Register support, (continued)
- [Qemu-devel] [PULL v2 03/21] hw/mips: add initial Global Config Register support, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 06/21] hw/mips/cps: create CPC block inside CPS, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 09/21] hw/mips_malta: move CPU creation to a separate function, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 16/21] hw/mips: implement ITC Storage - Bypass View, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 11/21] target-mips: enable CM GCR in MIPS64R6-generic CPU, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 12/21] hw/mips: implement ITC Configuration Tags and Storage Cells, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 19/21] hw/mips/cps: enable ITU for multithreading processors, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 20/21] target-mips: use CP0_CHECK for gen_m{f|t}hc0, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 14/21] hw/mips: implement ITC Storage - Empty/Full Sync and Try Views, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 15/21] hw/mips: implement ITC Storage - P/V Sync and Try Views, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 07/21] hw/mips_malta: remove CPUMIPSState from the write_bootloader(),
Leon Alrae <=
- [Qemu-devel] [PULL v2 08/21] hw/mips_malta: remove redundant irq and clock init, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 17/21] target-mips: check CP0 enabled for CACHE instruction also in R6, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 18/21] target-mips: make ITC Configuration Tags accessible to the CPU, Leon Alrae, 2016/03/30
- [Qemu-devel] [PULL v2 21/21] target-mips: add MAAR, MAARI register, Leon Alrae, 2016/03/30
- Re: [Qemu-devel] [PULL v2 00/21] target-mips queue for 2.6, Peter Maydell, 2016/03/30