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Re: [Qemu-devel] [PATCH v3 02/13] intel_iommu: set IR bit for ECAP regis
From: |
Jan Kiszka |
Subject: |
Re: [Qemu-devel] [PATCH v3 02/13] intel_iommu: set IR bit for ECAP register |
Date: |
Sat, 16 Apr 2016 19:30:25 -0700 |
User-agent: |
Mozilla/5.0 (X11; U; Linux i686 (x86_64); de; rv:1.8.1.12) Gecko/20080226 SUSE/2.0.0.12-1.1 Thunderbird/2.0.0.12 Mnenhy/0.7.5.666 |
On 2016-04-14 20:31, Peter Xu wrote:
> Enable IR in IOMMU Extended Capability register.
>
> Signed-off-by: Peter Xu <address@hidden>
> ---
> hw/i386/intel_iommu.c | 7 +++++++
> hw/i386/intel_iommu_internal.h | 2 ++
> 2 files changed, 9 insertions(+)
>
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 4b0558e..17668d6 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -24,6 +24,7 @@
> #include "exec/address-spaces.h"
> #include "intel_iommu_internal.h"
> #include "hw/pci/pci.h"
> +#include "hw/boards.h"
>
> /*#define DEBUG_INTEL_IOMMU*/
> #ifdef DEBUG_INTEL_IOMMU
> @@ -1941,6 +1942,8 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s,
> PCIBus *bus, int devfn)
> */
> static void vtd_init(IntelIOMMUState *s)
> {
> + MachineState *ms = MACHINE(qdev_get_machine());
> +
> memset(s->csr, 0, DMAR_REG_SIZE);
> memset(s->wmask, 0, DMAR_REG_SIZE);
> memset(s->w1cmask, 0, DMAR_REG_SIZE);
> @@ -1961,6 +1964,10 @@ static void vtd_init(IntelIOMMUState *s)
> VTD_CAP_SAGAW | VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS;
> s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO;
>
> + if (ms->iommu_intr) {
This cannot work, the field doesn't exit yet.
Please test bisectability after reordering patches.
Jan
> + s->ecap |= VTD_ECAP_IR;
> + }
> +
> vtd_reset_context_cache(s);
> vtd_reset_iotlb(s);
>
> diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
> index b648e69..5b98a11 100644
> --- a/hw/i386/intel_iommu_internal.h
> +++ b/hw/i386/intel_iommu_internal.h
> @@ -176,6 +176,8 @@
> /* (offset >> 4) << 8 */
> #define VTD_ECAP_IRO (DMAR_IOTLB_REG_OFFSET << 4)
> #define VTD_ECAP_QI (1ULL << 1)
> +/* Interrupt Remapping support */
> +#define VTD_ECAP_IR (1ULL << 3)
>
> /* CAP_REG */
> /* (offset >> 4) << 24 */
>
- [Qemu-devel] [PATCH v3 00/13] IOMMU: Enable interrupt remapping for Intel IOMMU, Peter Xu, 2016/04/14
- [Qemu-devel] [PATCH v3 01/13] intel_iommu: allow queued invalidation for IR, Peter Xu, 2016/04/14
- [Qemu-devel] [PATCH v3 02/13] intel_iommu: set IR bit for ECAP register, Peter Xu, 2016/04/14
- Re: [Qemu-devel] [PATCH v3 02/13] intel_iommu: set IR bit for ECAP register,
Jan Kiszka <=
- [Qemu-devel] [PATCH v3 03/13] acpi: add DMAR scope definition for root IOAPIC, Peter Xu, 2016/04/14
- [Qemu-devel] [PATCH v3 04/13] intel_iommu: define interrupt remap table addr register, Peter Xu, 2016/04/14
- [Qemu-devel] [PATCH v3 05/13] intel_iommu: handle interrupt remap enable, Peter Xu, 2016/04/14
- [Qemu-devel] [PATCH v3 06/13] intel_iommu: define several structs for IOMMU IR, Peter Xu, 2016/04/14
- [Qemu-devel] [PATCH v3 07/13] intel_iommu: provide helper function vtd_get_iommu, Peter Xu, 2016/04/14
- [Qemu-devel] [PATCH v3 08/13] intel_iommu: add IR translation faults defines, Peter Xu, 2016/04/14
- [Qemu-devel] [PATCH v3 09/13] intel_iommu: Add support for PCI MSI remap, Peter Xu, 2016/04/14
- [Qemu-devel] [PATCH v3 10/13] q35: ioapic: add support for emulated IOAPIC IR, Peter Xu, 2016/04/14
- [Qemu-devel] [PATCH v3 11/13] ioapic: introduce ioapic_entry_parse() helper, Peter Xu, 2016/04/14