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Re: [Qemu-devel] [PATCH 36/52] target-m68k: inline shift ops
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH 36/52] target-m68k: inline shift ops |
Date: |
Fri, 6 May 2016 10:53:05 -1000 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.0 |
On 05/04/2016 11:08 AM, Laurent Vivier wrote:
- if (count == 0) {
- count = 8;
- }
+ count = ((count - 1) & 0x7) + 1; /* 1..8 */
How is that clearer, or even simpler?
+ tcg_gen_setcond_i32(TCG_COND_EQ, QREG_CC_V, reg, zero);
+ /* adjust V: (1,0) -> (0,-1) */
+ tcg_gen_subi_i32(QREG_CC_V, QREG_CC_V, 1);
Better to use NE and neg.
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_const_i32(bits - 1 - count);
+
+ tcg_gen_shr_i32(QREG_CC_V, reg, t1);
+ tcg_gen_sar_i32(t0, reg, t1);
+ tcg_temp_free(t1);
+ tcg_gen_not_i32(t0, t0);
+
+ tcg_gen_setcond_i32(TCG_COND_EQ, QREG_CC_V, QREG_CC_V, zero);
+ tcg_gen_setcond_i32(TCG_COND_EQ, t0, t0, zero);
+ tcg_gen_or_i32(QREG_CC_V, QREG_CC_V, t0); /* V is !V here */
+
+ tcg_temp_free(t0);
+
+ /* adjust V: (1,0) -> (0,-1) */
+ tcg_gen_subi_i32(QREG_CC_V, QREG_CC_V, 1);
Can this be done more simply by creating a mask of sign bits, i.e.
tcg_gen_sari_i32(t0, reg, 31);
tcg_gen_shri_i32(t0, t0, bits - count);
tcg_gen_shri_i32(t1, reg, bits - count);
tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, t0, t1);
tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
r~
- [Qemu-devel] [PATCH 31/52] target-m68k: some bit ops cleanup, (continued)
- [Qemu-devel] [PATCH 31/52] target-m68k: some bit ops cleanup, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 32/52] target-m68k: bitfield ops, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 33/52] target-m68k: inline divu/divs, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 34/52] target-m68k: add 64bit mull, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 35/52] target-m68k: inline rotate ops, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 36/52] target-m68k: inline shift ops, Laurent Vivier, 2016/05/04
- Re: [Qemu-devel] [PATCH 36/52] target-m68k: inline shift ops,
Richard Henderson <=
- [Qemu-devel] [PATCH 37/52] target-m68k: add cas/cas2 ops, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 38/52] target-m68k: add linkl, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 39/52] target-m68k: movem, Laurent Vivier, 2016/05/04
- Re: [Qemu-devel] [PATCH 33/52] target-m68k: inline divu/divs, Richard Henderson, 2016/05/06
- [Qemu-devel] [PATCH 40/52] target-m68k: add exg ops, Laurent Vivier, 2016/05/04