[Qemu-devel] [PATCH v4 3/8] i.MX: Fix FEC code for MDIO operation selection

[Jean-Christophe Dubois]

According to the FEC chapter of i.MX25 reference manual

When writing the MMFR register, bit 29 and 28 select the requested operation.
 * 10 means read operation with valid MII mgmt frame
 * 11 means read operation with non compliant MII mgmt frame
 * 01 means write operation with valid MII mgmt frame
 * 00 means write operation with non compliant MII mgmt frame

So while bit 28 does change beween read/write for valid MII mgmt frame, the
mening is inverted for non compliant MII mgmt frame.

Bit 29 on the other hand means read/write whatever the type of mgmt frame
involved.

So this patch change the operation selection from bit 28 to bit 29 as it is
more generic.

Signed-off-by: Jean-Christophe Dubois <address@hidden>
---

Changes since v1: 
 * Not present on v1
 
Changes since v2:
 * Not present on v2

Changes since v3:
 * Not present on v3

 hw/net/imx_fec.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index e60e338..b3f5e4a 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -458,10 +458,10 @@ static void imx_fec_write(void *opaque, hwaddr addr,
     case 0x040: /* MMFR */
         /* store the value */
         s->mmfr = value;
-        if (extract32(value, 28, 1)) {
-            do_phy_write(s, extract32(value, 18, 9), extract32(value, 0, 16));
-        } else {
+        if (extract32(value, 29, 1)) {
             s->mmfr = do_phy_read(s, extract32(value, 18, 9));
+        } else {
+            do_phy_write(s, extract32(value, 18, 9), extract32(value, 0, 16));
         }
         /* raise the interrupt as the PHY operation is done */
         s->eir |= FEC_INT_MII;
-- 
2.7.4