Re: [Qemu-devel] ARM IRQ Generation

[Karthik]

Okay, understood. I`ll hold the IRQ line until CPU acknowledges the
interrupt.

By the way, is there a distinction between edge and level triggered
interrupt in the qemu or it is up to the emulation implementation?

Best regards,
Karthik






On Wed, May 25, 2016 at 6:04 PM, Peter Maydell <address@hidden>
wrote:

> On 25 May 2016 at 11:47, Karthik <address@hidden> wrote:
> > Hi,
> >
> > I am working on emulating an Spansion micro with ARM Cortex R5F Core.
> >
> > It has got an Interrupt Controller which accepts multiple interrupts and
> > generates the IRQ to the CPU based on register settings.
> >
> > Now an timer module calls the qemu_irq_pulse() to signal the Interrupt
> > Controller (IC). The interrupt handler in the IC is called with the
> correct
> > irq number with level 1 and immediately followed by level 0. The IC in
> turn
> > signals the CPU using qemu_set_irq with level 1 and 0.
> >
> > In this case the ARM CPU is not interrupted at all and there is no
> > exception generated, because the irq is lowered before the CPU is
> > interrupted.
>
> This sounds like your interrupt controller model is buggy. The
> IRQ and FIQ lines into the ARM CPU are level-triggered, so typically
> for an edge-triggered interrupt the interrupt controller will
> latch the fact that an interrupt has come in, and hold the IRQ
> line to the CPU high until the CPU acknowledges the interrupt
> in some way. Alternatively, your guest might be misconfiguring
> the interrupt controller to say that this timer module's interrupt
> is level-triggered when it's actually edge triggered. Or your
> timer device model might be buggy and using edge-triggered
> behaviour when it is supposed to be level-triggered.
>
> You need to check the hardware specs for how these various
> pieces are supposed to behave and see which one is out of
> line with its spec.
>
> thanks
> -- PMM
>