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Re: [Qemu-devel] [PATCH 3/4] target-tricore: Added new MOV instruction v
From: |
Bastian Koppelmann |
Subject: |
Re: [Qemu-devel] [PATCH 3/4] target-tricore: Added new MOV instruction variant |
Date: |
Mon, 30 May 2016 09:13:25 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.1.0 |
On 05/30/2016 12:59 AM, address@hidden wrote:
> From: Peer Adelt <address@hidden>
>
> Puts the content of data register D[a] into E[c][63:32] and the
> content of data register D[b] into E[c][31:0].
>
> Signed-off-by: Peer Adelt <address@hidden>
> ---
> target-tricore/translate.c | 4 ++++
> target-tricore/tricore-opcodes.h | 1 +
> 2 files changed, 5 insertions(+)
>
> diff --git a/target-tricore/translate.c b/target-tricore/translate.c
> index e66b433..2145f64 100644
> --- a/target-tricore/translate.c
> +++ b/target-tricore/translate.c
> @@ -6224,6 +6224,10 @@ static void decode_rr_accumulator(CPUTriCoreState
> *env, DisasContext *ctx)
> case OPC2_32_RR_MOV:
> tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
> break;
> + case OPC2_32_RR_MOV_EXT:
> + tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
> + tcg_gen_mov_tl(cpu_gpr_d[(r3 + 1)], cpu_gpr_d[r2]);
> + break;
Since this is a 1.6+ instruction, please check the hflags for the 1.6
ISA and raise an exception if 1.6+ ISA is not met. See OPC1_16_SRC_MOV_E
as an example.
Cheers,
Bastian