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Re: [Qemu-devel] [PATCH v6 08/11] target-avr: adding instruction transla
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v6 08/11] target-avr: adding instruction translation |
Date: |
Mon, 13 Jun 2016 09:06:29 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.1.0 |
On 06/12/2016 12:01 PM, Michael Rolnik wrote:
+void gen_push_ret(CPUAVRState *env, int ret)
+{
+ if (avr_feature(env, AVR_FEATURE_1_BYTE_PC)) {
+
+ TCGv t0 = tcg_const_i32((ret & 0x0000ff));
+
+ tcg_gen_qemu_st8(t0, cpu_sp, MMU_DATA_IDX);
+ tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
+
+ tcg_temp_free_i32(t0);
+ } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) {
+
+ TCGv t0 = tcg_const_i32((ret & 0x00ffff));
+
+ tcg_gen_qemu_st16(t0, cpu_sp, MMU_DATA_IDX);
+ tcg_gen_subi_tl(cpu_sp, cpu_sp, 2);
This stores to the wrong bytes. You need
tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW);
tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
+ } else if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) {
+
+ TCGv t0 = tcg_const_i32((ret & 0x0000ff));
+ TCGv t1 = tcg_const_i32((ret & 0xffff00) >> 8);
+
+ tcg_gen_qemu_st8(t0, cpu_sp, MMU_DATA_IDX);
+ tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
+
+ tcg_gen_qemu_st16(t1, cpu_sp, MMU_DATA_IDX);
+ tcg_gen_subi_tl(cpu_sp, cpu_sp, 2);
Similarly.
+void gen_pop_ret(CPUAVRState *env, TCGv ret)
+{
+ if (avr_feature(env, AVR_FEATURE_1_BYTE_PC)) {
+
+ tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
+ tcg_gen_qemu_ld8u(ret, cpu_sp, MMU_DATA_IDX);
+ } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) {
+
+ tcg_gen_addi_tl(cpu_sp, cpu_sp, 2);
+ tcg_gen_qemu_ld16u(ret, cpu_sp, MMU_DATA_IDX);
Similarly,
tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_BEUW);
tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
+ } else if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) {
+
+ TCGv t0 = tcg_temp_new_i32();
+
+ tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
+ tcg_gen_qemu_ld8u(ret, cpu_sp, MMU_DATA_IDX);
+
+ tcg_gen_addi_tl(cpu_sp, cpu_sp, 2);
+ tcg_gen_qemu_ld16u(t0, cpu_sp, MMU_DATA_IDX);
+
+ tcg_gen_shli_tl(t0, t0, 16);
+ tcg_gen_or_tl(ret, ret, t0);
You're putting t0 at the wrong end.
tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
tcg_gen_qemu_ld_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB);
tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_BEUW);
tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
tcg_gen_deposit_tl(ret, ret, t0, 16, 8);
r~
- [Qemu-devel] [PATCH v6 01/11] target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions, (continued)
- [Qemu-devel] [PATCH v6 01/11] target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions, Michael Rolnik, 2016/06/12
- [Qemu-devel] [PATCH v6 05/11] target-avr: adding AVR interrupt handling, Michael Rolnik, 2016/06/12
- [Qemu-devel] [PATCH v6 04/11] target-avr: adding instructions encodings, Michael Rolnik, 2016/06/12
- [Qemu-devel] [PATCH v6 06/11] target-avr: adding helpers for IN, OUT, SLEEP, WBR & unsupported instructions, Michael Rolnik, 2016/06/12
- [Qemu-devel] [PATCH v6 09/11] target-avr: updating translate.c to use instructions translation, Michael Rolnik, 2016/06/12
- [Qemu-devel] [PATCH v6 07/11] target-avr: adding instruction decoder, Michael Rolnik, 2016/06/12
- [Qemu-devel] [PATCH v6 11/11] target-avr: decoder generator. currently not used by the build, can be used manually, Michael Rolnik, 2016/06/12
- [Qemu-devel] [PATCH v6 10/11] target-avr: saving sreg, rampD, rampX, rampY, rampD, eind in HW representation saving cpu features, Michael Rolnik, 2016/06/12
- [Qemu-devel] [PATCH v6 08/11] target-avr: adding instruction translation, Michael Rolnik, 2016/06/12
- Re: [Qemu-devel] [PATCH v6 08/11] target-avr: adding instruction translation,
Richard Henderson <=
- Re: [Qemu-devel] [PATCH v6 00/11] 8bit AVR cores, Richard Henderson, 2016/06/13