[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v3 07/20] hw/intc/arm_gicv3: Move irq lines into GIC
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v3 07/20] hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structure |
Date: |
Tue, 14 Jun 2016 15:38:19 +0100 |
Move the GICv3 parent_irq and parent_fiq pointers into the
GICv3CPUState structure rather than giving them their own array.
This will make it easy to assert the IRQ and FIQ lines for a
particular CPU interface without having to know or calculate
the CPU index for the GICv3CPUState we are working on.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
---
hw/intc/arm_gicv3_common.c | 7 ++-----
include/hw/intc/arm_gicv3_common.h | 5 ++---
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index bf6949f..1557833 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -72,14 +72,11 @@ void gicv3_init_irqs_and_mmio(GICv3State *s,
qemu_irq_handler handler,
i = s->num_irq - GIC_INTERNAL + GIC_INTERNAL * s->num_cpu;
qdev_init_gpio_in(DEVICE(s), handler, i);
- s->parent_irq = g_malloc(s->num_cpu * sizeof(qemu_irq));
- s->parent_fiq = g_malloc(s->num_cpu * sizeof(qemu_irq));
-
for (i = 0; i < s->num_cpu; i++) {
- sysbus_init_irq(sbd, &s->parent_irq[i]);
+ sysbus_init_irq(sbd, &s->cpu[i].parent_irq);
}
for (i = 0; i < s->num_cpu; i++) {
- sysbus_init_irq(sbd, &s->parent_fiq[i]);
+ sysbus_init_irq(sbd, &s->cpu[i].parent_fiq);
}
memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s,
diff --git a/include/hw/intc/arm_gicv3_common.h
b/include/hw/intc/arm_gicv3_common.h
index bd364a7..cc6ac74 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -134,6 +134,8 @@ typedef struct GICv3CPUState GICv3CPUState;
struct GICv3CPUState {
GICv3State *gic;
CPUState *cpu;
+ qemu_irq parent_irq;
+ qemu_irq parent_fiq;
/* Redistributor */
uint32_t level; /* Current IRQ level */
@@ -168,9 +170,6 @@ struct GICv3State {
SysBusDevice parent_obj;
/*< public >*/
- qemu_irq *parent_irq;
- qemu_irq *parent_fiq;
-
MemoryRegion iomem_dist; /* Distributor */
MemoryRegion iomem_redist; /* Redistributors */
--
1.9.1
- Re: [Qemu-devel] [PATCH v3 16/20] hw/intc/arm_gicv3: Implement gicv3_cpuif_update(), (continued)
- [Qemu-devel] [PATCH v3 15/20] hw/intc/arm_gicv3: Implement GICv3 CPU interface registers, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 01/20] migration: Define VMSTATE_UINT64_2DARRAY, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 10/20] hw/intc/arm_gicv3: Implement functions to identify next pending irq, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 04/20] target-arm: Provide hook to tell GICv3 about changes of security state, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 14/20] hw/intc/arm_gicv3: Implement gicv3_set_irq(), Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 09/20] hw/intc/arm_gicv3: ARM GICv3 device framework, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 05/20] target-arm: Add mp-affinity property for ARM CPU class, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 07/20] hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structure,
Peter Maydell <=
- [Qemu-devel] [PATCH v3 03/20] target-arm: Define new arm_is_el3_or_mon() function, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 08/20] hw/intc/arm_gicv3: Add vmstate descriptors, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 12/20] hw/intc/arm_gicv3: Implement GICv3 redistributor registers, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 06/20] hw/intc/arm_gicv3: Add state information, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 11/20] hw/intc/arm_gicv3: Implement GICv3 distributor registers, Peter Maydell, 2016/06/14