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[Qemu-devel] [PULL 13/22] hw/intc/arm_gicv3: Wire up distributor and red
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 13/22] hw/intc/arm_gicv3: Wire up distributor and redistributor MMIO regions |
Date: |
Fri, 17 Jun 2016 15:25:43 +0100 |
Wire up the MMIO functions exposed by the distributor and the
redistributor into MMIO regions exposed by the GICv3 device.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Tested-by: Shannon Zhao <address@hidden>
Message-id: address@hidden
---
hw/intc/arm_gicv3.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c
index 171d587..4c1fbb6 100644
--- a/hw/intc/arm_gicv3.c
+++ b/hw/intc/arm_gicv3.c
@@ -324,6 +324,19 @@ static void arm_gicv3_post_load(GICv3State *s)
gicv3_cache_all_target_cpustates(s);
}
+static const MemoryRegionOps gic_ops[] = {
+ {
+ .read_with_attrs = gicv3_dist_read,
+ .write_with_attrs = gicv3_dist_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ },
+ {
+ .read_with_attrs = gicv3_redist_read,
+ .write_with_attrs = gicv3_redist_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ }
+};
+
static void arm_gic_realize(DeviceState *dev, Error **errp)
{
/* Device instance realize function for the GIC sysbus device */
@@ -337,7 +350,7 @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
return;
}
- gicv3_init_irqs_and_mmio(s, gicv3_set_irq, NULL);
+ gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops);
}
static void arm_gicv3_class_init(ObjectClass *klass, void *data)
--
1.9.1
- [Qemu-devel] [PULL 03/22] target-arm: Define new arm_is_el3_or_mon() function, (continued)
- [Qemu-devel] [PULL 03/22] target-arm: Define new arm_is_el3_or_mon() function, Peter Maydell, 2016/06/17
- [Qemu-devel] [PULL 04/22] target-arm: Provide hook to tell GICv3 about changes of security state, Peter Maydell, 2016/06/17
- [Qemu-devel] [PULL 05/22] target-arm: Add mp-affinity property for ARM CPU class, Peter Maydell, 2016/06/17
- [Qemu-devel] [PULL 07/22] hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structure, Peter Maydell, 2016/06/17
- [Qemu-devel] [PULL 01/22] migration: Define VMSTATE_UINT64_2DARRAY, Peter Maydell, 2016/06/17
- [Qemu-devel] [PULL 02/22] bitops.h: Implement half-shuffle and half-unshuffle ops, Peter Maydell, 2016/06/17
- [Qemu-devel] [PULL 08/22] hw/intc/arm_gicv3: Add vmstate descriptors, Peter Maydell, 2016/06/17
- [Qemu-devel] [PULL 12/22] hw/intc/arm_gicv3: Implement GICv3 redistributor registers, Peter Maydell, 2016/06/17
- [Qemu-devel] [PULL 06/22] hw/intc/arm_gicv3: Add state information, Peter Maydell, 2016/06/17
- [Qemu-devel] [PULL 09/22] hw/intc/arm_gicv3: ARM GICv3 device framework, Peter Maydell, 2016/06/17
- [Qemu-devel] [PULL 13/22] hw/intc/arm_gicv3: Wire up distributor and redistributor MMIO regions,
Peter Maydell <=
- [Qemu-devel] [PULL 19/22] target-arm/machine.c: Allow user to request GICv3 emulation, Peter Maydell, 2016/06/17
- [Qemu-devel] [PULL 16/22] hw/intc/arm_gicv3: Implement gicv3_cpuif_update(), Peter Maydell, 2016/06/17
- [Qemu-devel] [PULL 11/22] hw/intc/arm_gicv3: Implement GICv3 distributor registers, Peter Maydell, 2016/06/17
- [Qemu-devel] [PULL 22/22] ACPI: ARM: Present GIC version in MADT table, Peter Maydell, 2016/06/17
- [Qemu-devel] [PULL 21/22] hw/timer: Add value matching support to aspeed_timer, Peter Maydell, 2016/06/17
- [Qemu-devel] [PULL 15/22] hw/intc/arm_gicv3: Implement GICv3 CPU interface registers, Peter Maydell, 2016/06/17
- [Qemu-devel] [PULL 20/22] target-arm/monitor.c: Advertise emulated GICv3 in capabilities, Peter Maydell, 2016/06/17
- [Qemu-devel] [PULL 18/22] hw/intc/arm_gicv3: Add IRQ handling CPU interface registers, Peter Maydell, 2016/06/17
- [Qemu-devel] [PULL 14/22] hw/intc/arm_gicv3: Implement gicv3_set_irq(), Peter Maydell, 2016/06/17
- [Qemu-devel] [PULL 10/22] hw/intc/arm_gicv3: Implement functions to identify next pending irq, Peter Maydell, 2016/06/17