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[Qemu-devel] [PATCH v10 07/26] intel_iommu: set IR bit for ECAP register
From: |
Peter Xu |
Subject: |
[Qemu-devel] [PATCH v10 07/26] intel_iommu: set IR bit for ECAP register |
Date: |
Tue, 21 Jun 2016 15:47:35 +0800 |
Enable IR in IOMMU Extended Capability register.
Signed-off-by: Peter Xu <address@hidden>
---
hw/i386/intel_iommu.c | 6 ++++++
hw/i386/intel_iommu_internal.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index b170f97..e216fd3 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -1948,6 +1948,8 @@ static AddressSpace *vtd_find_add_as(X86IOMMUState
*x86_iommu, PCIBus *bus,
*/
static void vtd_init(IntelIOMMUState *s)
{
+ X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
+
memset(s->csr, 0, DMAR_REG_SIZE);
memset(s->wmask, 0, DMAR_REG_SIZE);
memset(s->w1cmask, 0, DMAR_REG_SIZE);
@@ -1968,6 +1970,10 @@ static void vtd_init(IntelIOMMUState *s)
VTD_CAP_SAGAW | VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS;
s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO;
+ if (x86_iommu->intr_supported) {
+ s->ecap |= VTD_ECAP_IR;
+ }
+
vtd_reset_context_cache(s);
vtd_reset_iotlb(s);
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index b648e69..5b98a11 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -176,6 +176,8 @@
/* (offset >> 4) << 8 */
#define VTD_ECAP_IRO (DMAR_IOTLB_REG_OFFSET << 4)
#define VTD_ECAP_QI (1ULL << 1)
+/* Interrupt Remapping support */
+#define VTD_ECAP_IR (1ULL << 3)
/* CAP_REG */
/* (offset >> 4) << 24 */
--
2.4.11
- [Qemu-devel] [PATCH v10 00/26] IOMMU: Enable interrupt remapping for Intel IOMMU, Peter Xu, 2016/06/21
- [Qemu-devel] [PATCH v10 01/26] x86-iommu: introduce parent class, Peter Xu, 2016/06/21
- [Qemu-devel] [PATCH v10 02/26] x86-iommu: provide x86_iommu_get_default, Peter Xu, 2016/06/21
- [Qemu-devel] [PATCH v10 04/26] x86-iommu: introduce "intremap" property, Peter Xu, 2016/06/21
- [Qemu-devel] [PATCH v10 03/26] x86-iommu: q35: generalize find_add_as(), Peter Xu, 2016/06/21
- [Qemu-devel] [PATCH v10 05/26] acpi: enable INTR for DMAR report structure, Peter Xu, 2016/06/21
- [Qemu-devel] [PATCH v10 06/26] intel_iommu: allow queued invalidation for IR, Peter Xu, 2016/06/21
- [Qemu-devel] [PATCH v10 07/26] intel_iommu: set IR bit for ECAP register,
Peter Xu <=
- [Qemu-devel] [PATCH v10 08/26] acpi: add DMAR scope definition for root IOAPIC, Peter Xu, 2016/06/21
- [Qemu-devel] [PATCH v10 09/26] intel_iommu: define interrupt remap table addr register, Peter Xu, 2016/06/21
- [Qemu-devel] [PATCH v10 10/26] intel_iommu: handle interrupt remap enable, Peter Xu, 2016/06/21
- [Qemu-devel] [PATCH v10 11/26] intel_iommu: define several structs for IOMMU IR, Peter Xu, 2016/06/21
- [Qemu-devel] [PATCH v10 12/26] intel_iommu: add IR translation faults defines, Peter Xu, 2016/06/21
- [Qemu-devel] [PATCH v10 13/26] intel_iommu: Add support for PCI MSI remap, Peter Xu, 2016/06/21
- [Qemu-devel] [PATCH v10 14/26] q35: ioapic: add support for emulated IOAPIC IR, Peter Xu, 2016/06/21
- [Qemu-devel] [PATCH v10 15/26] ioapic: introduce ioapic_entry_parse() helper, Peter Xu, 2016/06/21
- [Qemu-devel] [PATCH v10 16/26] intel_iommu: add support for split irqchip, Peter Xu, 2016/06/21