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[Qemu-devel] [PATCH v9 00/10] 8bit AVR cores
From: |
Michael Rolnik |
Subject: |
[Qemu-devel] [PATCH v9 00/10] 8bit AVR cores |
Date: |
Wed, 22 Jun 2016 12:51:45 +0300 |
This series of patches adds 8bit AVR cores to QEMU.
All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested
yet.
However I was able to execute simple code with functions. e.g fibonacci
calculation.
This series of patches include a non real, sample board.
No fuses support yet. PC is set to 0 at reset.
the patches include the following
1. just a basic 8bit AVR CPU, without instruction decoding or translation
2. CPU features which allow define the following 8bit AVR cores
avr1
avr2 avr25
avr3 avr31 avr35
avr4
avr5 avr51
avr6
xmega2 xmega4 xmega5 xmega6 xmega7
3. a definition of sample machine with SRAM, FLASH and CPU which allows to
execute simple code
4. encoding for all AVR instructions
5. interrupt handling
6. helpers for IN, OUT, SLEEP, WBR & unsupported instructions
7. a decoder which given an opcode decides what istruction it is
8. translation of AVR instruction into TCG
9. all features together
changes since v3
1. rampD/X/Y/Z registers are encoded as 0x00ff0000 (instead of 0x000000ff) for
faster address manipulaton
2. ffs changed to ctz32
3. duplicate code removed at avr_cpu_do_interrupt
4. using andc instead of not + and
5. fixing V flag calculation in varios instructions
6. freeing local variables in PUSH
7. tcg_const_local_i32 -> tcg_const_i32
8. using sextract32 instead of my implementation
9. fixing BLD instruction
10.xor(r) instead of 0xff - r at COM
11.fixing MULS/MULSU not to modify inputs' content
12.using SUB for NEG
13.fixing tcg_gen_qemu_ld/st call in XCH
changes since v4
1. target is now defined as big endian in order to optimize push_ret/pop_ret
2. all style warnings are fixed
3. adding cpu_set/get_sreg functions
4. simplifying gen_goto_tb as there is no real paging
5. env->pc -> env->pc_w
6. making flag dump more compact
7. more spacing
8. renaming CODE/DATA_INDEX -> MMU_CODE/DATA_IDX
9. removing avr_set_feature
10. SPL/SPH set bug fix
11. switching stb_phys to cpu_stb_data
12. cleaning up avr_decode
13. saving sreg, rampD/X/Y/Z, eind in HW format (savevm)
14. saving CPU features (savevm)
changes since v5
1. BLD bug fix
2. decoder generator is added
chages since v6
1. using cpu_get_sreg/cpu_set_sreg in
avr_cpu_gdb_read_register/avr_cpu_gdb_write_register
2. configure the target as little endian because otherwise GDB does not work
3. fixing and testing gen_push_ret/gen_pop_ret
changes since v7
1. folding back v6
2. logging at helper_outb and helper_inb are done for non supported yet
registers only
3. MAINTAINERS updated
changes since v8
1. removing hw/avr from hw/Makefile.obj as it should not be built for all
2. making linux compilable
3. testing on
a. Mac, Apple LLVM version 7.0.0
b. Ubuntu 12.04, gcc 4.9.2
c. Fedora 23, gcc 5.3.1
4. folding back some patches
5. translation bug fixes for ADIW, SBIW, XOR instructions
6. propper handling of cpu register writes though memory
Michael Rolnik (10):
target-avr: AVR cores support is added. 1. basic CPU structure
2. registers 3. no instructions 4. saving
sreg, rampD, rampX, rampY, rampD, eind in HW representation saving
cpu features
target-avr: adding AVR CPU features/flavors
target-avr: adding a sample AVR board
target-avr: adding instructions encodings
target-avr: adding AVR interrupt handling
target-avr: adding helpers for IN, OUT, SLEEP, WBR & unsupported
instructions
target-avr: adding instruction decoder
target-avr: adding instruction translation
target-avr: updating translate.c to use instructions translation
target-avr: decoder generator. currently not used by the build, can be
used manually
MAINTAINERS | 6 +
arch_init.c | 2 +
configure | 5 +
default-configs/avr-softmmu.mak | 21 +
hw/avr/Makefile.objs | 21 +
hw/avr/sample-io.c | 227 +++
hw/avr/sample.c | 116 ++
include/disas/bfd.h | 6 +
include/sysemu/arch_init.h | 1 +
target-avr/Makefile.objs | 25 +
target-avr/cpu-qom.h | 84 +
target-avr/cpu.c | 609 +++++++
target-avr/cpu.h | 220 +++
target-avr/cpugen/CMakeLists.txt | 38 +
target-avr/cpugen/README.md | 17 +
target-avr/cpugen/cpu/avr.yaml | 214 +++
target-avr/cpugen/src/CMakeLists.txt | 62 +
target-avr/cpugen/src/cpugen.cpp | 460 +++++
target-avr/cpugen/src/utils.cpp | 27 +
target-avr/cpugen/src/utils.h | 79 +
target-avr/cpugen/xsl/decode.c.xsl | 103 ++
target-avr/cpugen/xsl/translate-inst.h.xsl | 118 ++
target-avr/cpugen/xsl/utils.xsl | 108 ++
target-avr/decode.c | 693 ++++++++
target-avr/gdbstub.c | 84 +
target-avr/helper.c | 340 ++++
target-avr/helper.h | 27 +
target-avr/machine.c | 117 ++
target-avr/machine.h | 21 +
target-avr/translate-inst.c | 2636 ++++++++++++++++++++++++++++
target-avr/translate-inst.h | 762 ++++++++
target-avr/translate.c | 271 +++
target-avr/translate.h | 119 ++
33 files changed, 7639 insertions(+)
create mode 100644 default-configs/avr-softmmu.mak
create mode 100644 hw/avr/Makefile.objs
create mode 100644 hw/avr/sample-io.c
create mode 100644 hw/avr/sample.c
create mode 100644 target-avr/Makefile.objs
create mode 100644 target-avr/cpu-qom.h
create mode 100644 target-avr/cpu.c
create mode 100644 target-avr/cpu.h
create mode 100644 target-avr/cpugen/CMakeLists.txt
create mode 100644 target-avr/cpugen/README.md
create mode 100644 target-avr/cpugen/cpu/avr.yaml
create mode 100644 target-avr/cpugen/src/CMakeLists.txt
create mode 100644 target-avr/cpugen/src/cpugen.cpp
create mode 100644 target-avr/cpugen/src/utils.cpp
create mode 100644 target-avr/cpugen/src/utils.h
create mode 100644 target-avr/cpugen/xsl/decode.c.xsl
create mode 100644 target-avr/cpugen/xsl/translate-inst.h.xsl
create mode 100644 target-avr/cpugen/xsl/utils.xsl
create mode 100644 target-avr/decode.c
create mode 100644 target-avr/gdbstub.c
create mode 100644 target-avr/helper.c
create mode 100644 target-avr/helper.h
create mode 100644 target-avr/machine.c
create mode 100644 target-avr/machine.h
create mode 100644 target-avr/translate-inst.c
create mode 100644 target-avr/translate-inst.h
create mode 100644 target-avr/translate.c
create mode 100644 target-avr/translate.h
--
2.4.9 (Apple Git-60)
- [Qemu-devel] [PATCH v9 00/10] 8bit AVR cores,
Michael Rolnik <=
- [Qemu-devel] [PATCH v9 03/10] target-avr: adding a sample AVR board, Michael Rolnik, 2016/06/22
- [Qemu-devel] [PATCH v9 05/10] target-avr: adding AVR interrupt handling, Michael Rolnik, 2016/06/22
- [Qemu-devel] [PATCH v9 01/10] target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions 4. saving sreg, rampD, rampX, rampY, rampD, eind in HW representation saving cpu features, Michael Rolnik, 2016/06/22
- [Qemu-devel] [PATCH v9 04/10] target-avr: adding instructions encodings, Michael Rolnik, 2016/06/22
- [Qemu-devel] [PATCH v9 06/10] target-avr: adding helpers for IN, OUT, SLEEP, WBR & unsupported instructions, Michael Rolnik, 2016/06/22
- [Qemu-devel] [PATCH v9 07/10] target-avr: adding instruction decoder, Michael Rolnik, 2016/06/22
- [Qemu-devel] [PATCH v9 02/10] target-avr: adding AVR CPU features/flavors, Michael Rolnik, 2016/06/22
- [Qemu-devel] [PATCH v9 09/10] target-avr: updating translate.c to use instructions translation, Michael Rolnik, 2016/06/22
- [Qemu-devel] [PATCH v9 10/10] target-avr: decoder generator. currently not used by the build, can be used manually, Michael Rolnik, 2016/06/22
- [Qemu-devel] [PATCH v9 08/10] target-avr: adding instruction translation, Michael Rolnik, 2016/06/22